NCP1271 datasheet(12/19 Pages) ONSEMI

Part #	NCP1271

Description	Soft?뭆kip Mode Standby PWM Controller with Adjustable Skip Level and External Latch

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Manufacturer	ONSEMI [ON Semiconductor]

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NCP1271

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external components during a fault event. After the second

cycle, the controller tries to restart the application. If the

restart is not successful, then the process is repeated.

During this mode, VCC never drops below the 4 V latch

reset level. Therefore, latched faults will not be cleared

unless the application is unplugged from the AC line (i.e.,

Vbulk discharges).

Figure 25 shows a timing diagram of the VCC double

hiccup operation. Note that at each restart attempt, a soft

start is issued to minimize stress.

Figure 25. VCC Double Hiccup Operation in a Fault

Condition

5.8 V

12.6 V

9.1 V

D

tstartup

time

CC

Supply voltage, V

time

Drain current, I

Switching is missing in

every two VCC hiccup cycles

featuring a “double−hiccup”

VCC Capacitor

As stated earlier, the NCP1271 enters a fault condition

when the feedback pin is open (i.e. FB is greater than 3 V)

for 130 ms or VCC drops below VCC(off) (9.1 V typical).

Therefore, to take advantage of these features, the VCC

capacitor needs to be sized so that operation can be

maintained in the absence of the auxiliary winding for at

least 130 ms.

The controller typically consumes 2.3 mA at a 65 kHz

frequency with a 1 nF switch gate capacitance. Therefore,

to ensure at least 130 ms of operation, equation 1 can be

used to calculate that at least an 85

mF capacitor would be

necessary.

tstartup +

CVCCDV

ICC1

+

85 mF · (12.6 V−9.1 V)

2.3 mA

+ 130 ms

(eq. 1)

If the 130 ms timer feature will not be used, then the

capacitance value needs to at least be large enough for the

output to charge up to a point where the auxiliary winding

can supply VCC. Figure 26 describes different startup

scenarios with different VCC capacitor values. If the VCC

cap is too small, the application fails to start because the

bias supply voltage cannot be established before VCC is

reduced to the VCC(off) level.

Figure 26. Different Startup Scenarios of the

Circuits with Different VCC Capacitors

time

V

Vout

CC

time

VCC

out

V

9.1 V

12.6 V

5.8 V

9.1 V

12.6 V

tstartup

0.6 V

Output waveforms with a large enough VCC capacitor

Output waveforms with too small of a VCC capacitor

Desired level of Vout

It is highly recommended that the VCC capacitor be as

close as possible to the VCC and ground pins of the product

to reduce switching noise. A small bypass capacitor on this

pin is also recommended. If the switching noise is large

enough, it could potentially cause VCCto go below VCC(off)

and force a restart of the controller.

It is also recommended to have a margin between the

winding bias voltage and VCC(off) so that all possible

transient swings of the auxiliary winding are allowed. In

standby mode, the VCC voltage swing can be higher due to

the low−frequency skip−cycle operation. The VCC

capacitor also affects this swing. Figure 27 illustrates the

possible swings.

Figure 27. Timing Diagram of Standby Condition

V

FB

D

9.1 V

CC

skip

time

Supply voltage, V

time

Feedback pin voltage, V

time

Drain current, I

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NCP1271 Datasheet(PDF) 12 Page - ON Semiconductor

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