NCN4557

http://onsemi.com

10

18 k

CRD_I/O

14 k

I/O

LOGIC

IO/CONTROL

GND

GND

200 ns

200 ns

Q1

Q2

Q3

Figure 10. Basic I/O line Interface

The typical waveform provided in Figure 11 shows how

the accelerator operates. During the first 200 ns (typical),

the slope of the rise time is solely a function of the pullup

resistor associated with the stray capacitance. During this

period, the PMOS devices are not activated since the input

providing a low impedance to charge the capacitance, thus

increasing the rise time as depicted in Figure 11. The same

mechanism applies for the opposite side of the line to make

sure the system is optimum.

Figure 11. CRD_IO Typical Rise and Fall Times

with Stray Capacitance > 30 pF

(33 pF capacitor connected on the board)

Powerup Sequence

The powerup sequence makes sure all the card−related

slope. The Powerup sequence is activated by setting the

ENABLE Boolean signal HIGH. CRD_RST, CRD_CLK

and CRD_I/O are maintained LOW during the activation

3.0 V). Figure 7 shows the typical NCN4557 activation

sequence.

About 800

voltage value, CRD_IO and CRD_RST are released.

CRD_CLK is enabled during the rising slope of the

second clock cycle after CRD_IO and CRD_RST are

enabled.

Figure 12. NCN4557 Power−Up

CRD_RSTA/B

CRD_IOA/B

CRD_CLKA/B

ENABLE

2nd Rise Edge After

CRD_IOA/B Rising

In all cases the application software is responsible for the

smart card signal sequence (contact activation sequence,

cold reset and warm reset sequences).

Powerdown Sequence

The NCN4557 provides a powerdown sequence which is

activated by setting the ENABLE Boolean signal LOW.

The communication I/O session is terminated immediately

according to the ISO7816 and EMV specifications as

depicted in Figures 8 and 13.

ISO7816 Sequence:

ENABLE is set LOW unless CRD_CLK is already in