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AD7674 Datasheet(PDF) 22 Page - Analog Devices

Part # AD7674
Description  18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7674 Datasheet(HTML) 22 Page - Analog Devices

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AD7674
In Read during Conversion mode, the serial clock and data
toggle at appropriate instants, minimizing potential feedthrough
between digital activity and critical conversion decisions.
MASTER SERIAL INTERFACE
Internal Clock
The AD7674 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7674 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. Figure 40 and Figure 41 show
the detailed timing diagrams of these two modes.
In Read after Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns low after the 18 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
Usually, because the AD7674 is used with a fast throughput, the
Master Read during Conversion mode is the most
recommended serial mode.
t3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
12
3
16
17
18
D17
D16
D2
D1
D0
X
EXT/INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t14
t20
t15
t16
t22
t23
t29
t28
t18
t19
t21
t30
t25
t24
t26
t27
03083-0-040
Figure 40. Master Serial Data Timing for Reading (Read after Convert)
Rev. 0 | Page 22 of 28


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