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AD7674 Datasheet(PDF) 21 Page - Analog Devices |
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AD7674 Datasheet(HTML) 21 Page - Analog Devices |
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21 / 28 page  AD7674 Rev. 0 | Page 21 of 28 DIGITAL INTERFACE The AD7674 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The AD7674 digital interface also accommodates both 3 V and 5 V logic by simply connecting the AD7674’s OVDD supply pin to the host system interface digital supply. Finally, by using the OB/2C input pin in any mode but 18-bit interface mode, both twos complement and straight binary coding can be used. The two signals, CS and RD, control the interface. When at least one of these signals is high, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7674 in multicircuit applications, and is held low in a single AD7674 design. RD is generally used to enable the conversion result on the data bus. t9 RESET DATA BUS BUSY CNVST t8 03083-0-035 Figure 35. RESET Timing CNVST BUSY DATA BUS CS = RD = 0 PREVIOUS CONVERSION DATA NEW DATA t1 t10 t4 t3 t11 03083-0-036 Figure 36. Master Parallel Data Timing for Reading (Continuous Read) PARALLEL INTERFACE The AD7674 is configured to use the parallel interface with an 18-bit, a 16-bit, or an 8-bit bus width, according to Table 7. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in Figure 37 and Figure 38, respectively. When the data is read during the conversion, however, it is recommended that it is read only during the first half of the conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. Refer to Table 7 for a detailed description of the different options available. DATA BUS t12 t13 BUSY CS RD CURRENT CONVERSION 03083-0-037 Figure 37. Slave Parallel Data Timing for Reading (Read after Convert) CS = 0 CNVST, RD t1 PREVIOUS CONVERSION DATA BUS t12 t13 BUSY t4 t3 03083-0-038 Figure 38. Slave Parallel Data Timing for Reading (Read during Convert) CS RD A0, A1 PINS D[15:8] PINS D[7:0] HI-Z HI-Z HIGH BYTE LOW BYTE LOW BYTE HIGH BYTE HI-Z HI-Z t12 t12 t13 03083-0-039 Figure 39. 8-Bit and 16-Bit Parallel Interface SERIAL INTERFACE The AD7674 is configured to use the serial interface when MODE0 and MODE1 are held high. The AD7674 outputs 18 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 18 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edge of the data clock. |
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