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AD7674 Datasheet(PDF) 20 Page - Analog Devices |
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AD7674 Datasheet(HTML) 20 Page - Analog Devices |
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20 / 28 page  AD7674 Rev. 0 | Page 20 of 28 SAMPLING RATE (SPS) 1000000 1M 100000 10000 1000 100 10 1 0.1 100k 10k 1k 100 1 WARP/NORMAL 10 PDBUF HIGH 03083-0-033 IMPULSE Power Supply The AD7674 uses three sets of power supply pins: an analog 5 V supply (AVDD), a digital 5 V core supply (DVDD), and a digital output interface supply (OVDD). The OVDD supply defines the output logic level and allows direct interface with any logic working between 2.7 V and DVDD + 0.3 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply, as shown in Figure 27. The AD7674 is independent of power supply sequencing once OVDD does not exceed DVDD by more than 0.3 V, and is therefore free from supply voltage induced latch-up. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 32. Figure 33. Power Dissipation vs. Sample Rate FREQUECY (kHz) 70 65 40 100 1000 10000 110 60 55 50 45 03083-0-032 CONVERSION CONTROL Figure 34 shows the detailed timing diagrams of the conversion process. The AD7674 is controlled by the CNVST signal, which initiates conversion. Once initiated, it cannot be restarted or aborted, even by PD, until the conversion is complete. The CNVST signal operates independently of CS and RD signals. CNVST t1 t2 MODE ACQUIRE CONVERT ACQUIRE CONVERT t7 t8 BUSY t4 t3 t5 t6 03083-0-034 Figure 32. PSRR vs. Frequency POWER DISSIPATION VERSUS THROUGHPUT Figure 34. Basic Conversion Timing In Impulse mode, the AD7674 automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low, which allows for a significant power savings when the conversion rate is reduced, as shown in Figure 33. This feature makes the AD7674 ideal for very low power battery applications. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (DVDD and DGND), and OVDD should not exceed DVDD by more than 0.3 V. Although CNVST is a digital signal, it should be designed with special care with fast, clean edges and levels with minimum overshoot and undershoot or ringing. For applications where SNR is critical, the CNVST signal should have very low jitter. This may be achieved by using a dedicated oscillator for CNVST generation, or to clock it with a high frequency low jitter clock, as shown in Figure 27. In Impulse mode, conversions can be initiated automatically. If CNVST is held low when BUSY goes low, the AD7674 controls the acquisition phase and automatically initiates a new conversion. By keeping CNVST low, the AD7674 keeps the conversion process running by itself. Note that the analog input has to be settled when BUSY goes low. Also, at power-up, CNVST should be brought low once to initiate the conversion process. In this mode, the AD7674 could sometimes run slightly faster than the guaranteed limits of 570 kSPS in Impulse mode. This feature does not exist in Warp or Normal modes. |
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