AD7674

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44

39 38 37

43 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

AGND

CNVST

PD

RESET

CS

RD

DGND

AGND

AVDD

MODE0

MODE1

D0/OB/2C

WARP

IMPULSE

NC = NO CONNECT

D1/A0

D2/A1

D3

D4/DIVSCLK[0]

BUSY

D17

D16

D15

AD7674

D5/DIVSCLK[1]

D14

03083–0–004

Figure 4. 48-Lead LQFP and 48-Lead LFCSP (ST-48 and CP-48)

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

1, 44

AGND

P

Analog Power Ground Pin.

2, 47

AVDD

P

Input Analog Power Pins. Nominally 5 V.

3

MODE0

DI

Data Output Interface Mode Selection.

4

MODE1

DI

Data Output Interface Mode Selection:

Interface MODE #

MODE1

MODE0

Description

0

0

0

18-Bit Interface

1

0

1

16-Bit Interface

2

1

0

Byte Interface

3

1

1

Serial Interface

5

D0/OB/2C

DI/O

When MODE = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the data

coding is straight binary. In all other modes, this pin allows choice of straight binary/binary twos

complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted,

resulting in a twos complement output from its internal shift register.

6

WARP

DI

Conversion Mode Selection. When this input is HIGH and the IMPULSE pin is LOW, WARP selects the

fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied

in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the

minimum conversion rate.

7

IMPULSE

DI

Conversion Mode Selection. When this input is HIGH and the WARP pin is LOW, IMPULSE selects a

reduced power mode. In this mode, the power dissipation is approximately proportional to the

sampling rate. When WARP and IMPULSE pins are LOW, the NORMAL mode is selected.

8

D1/A0

DI/O

When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all other

modes, this input pin controls the form in which data is output, as shown in Table 7.

9

D2/A1

DI/O

When MODE = 0 or 1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data output

bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7.

10

D3

DO

In all modes except MODE = 3, this output is used as Bit 3 of the parallel port data output bus. This pin is

always an output, regardless of the interface mode.

11, 12

D[4:5]or

DIVSCLK[0:

1]

DI/O

In all modes except MODE = 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus.

When MODE = 3 (serial mode), when EXT/INT is LOW and RDC/SDIN is LOW (serial master read after

convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock

that clocks the data output. In other serial modes, these pins are not used.