IS61SP6464

Integrated Silicon Solution, Inc. — 1-800-379-4774

17

Rev. A

04/17/01

-133 MHz

-117 MHz

-100 MHz

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Cycle Time

7.5

—

8.5

—

10

—

ns

Clock High Time

3

—

3.4

—

4

—

ns

Clock Low Time

3

—

3.4

—

4

—

ns

Clock Access Time

—

5

—

5

—

5ns

Clock High to Output Invalid

0

——

—

2.5

—

ns

Clock High to Output Low-Z

0

—

0

—

0

—

ns

Clock High to Output High-Z

1.5

7.5

1.5

8.5

2

5

ns

Output Enable to Output Valid

—

5

—

4

—

5ns

Output Disable to Output Invalid

0

—

0

—

0

—

ns

Output Enable to Output Low-Z

0

—

0

—

0

—

ns

Output Disable to Output High-Z

——

——

25

ns

Address Setup Time

2.5

—

2.5

—

2.5

—

ns

Address Status Setup Time

2.5

—

2.5

—

2.5

—

ns

Chip Enable Setup Time

2.5

—

2.5

—

2.5

—

ns

Address Hold Time

0.5

—

0.5

—

0.5

—

ns

Address Status Hold Time

0.5

—

0.5

—

0.5

—

ns

Chip Enable Hold Time

0.5

—

0.5

—

0.5

—

ns

2

—

2

—

2

—

cyc

2

—

2

—

2

—

cyc

Notes:

1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data

retention is guaranteed when ZZ is asserted and clock remains active.

2.

ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.

3. Guaranteed but not 100% tested. This parameter is periodically sampled.

4. Tested with load in Figure 2.