Nexperia

HEF4518B

Dual BCD counter

VM

VM

tW

tW

10 %

90 %

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

90 %

10 %

tf

tr

tr

tf

001aaj781

a. Input waveforms

VDD

VI

VO

001aag182

DUT

CL

RT

G

b. Test circuit

Test data is given in Table 10.

Definitions for test circuit:

CL = Load capacitance including jig and probe capacitance;

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

Fig. 6. Test circuit for measuring switching times

Table 10. Test data

Supply

Input

Load

VDD

VI

tr, tf

CL

5 V to 15 V

VSS or VDD

≤ 20 ns

50 pF

HEF4518B

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 9 — 3 December 2021

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