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IRS2166DSPBF Datasheet(PDF) 11 Page - International Rectifier |
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IRS2166DSPBF Datasheet(HTML) 11 Page - International Rectifier |
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11 / 20 page  IRS2166D(S)PbF www.irf.com Page 11 VCC is above VCCUV+ (ballast power on) and SD is pulled above 5.0 V (VSDTH+) and back below 3.0 V (VSDTH-) (lamp re-insertion), the IC will enter preheat mode and begin oscillating again. The current sense function will force the IC to enter fault mode only after the voltage at the CS pin has been greater than 1.20 V (VCSTH+) for 100 (nEVENTS) consecutive cycles of LO. The over-current function at the CS pin (see Fig. 5) will only consecutive cycles of LO. The over- current function at the CS pin (see Fig. 5) will only work with over-current events that occur during the LO on-time. If the over-current faults are not consecutive, then the internal fault counter will count back down each cycle when there is no fault present. Should an over-current fault occur only for a few cycles and then not occur again, the counter will eventually count back down to zero. The over-current fault counter is enabled during preheat and ignition modes and disabled during run mode. During run mode, the IC will enter fault mode after a single over- current event at the CS pin. II. PFC Section Functional Description In most electronic ballasts it is necessary to have the circuit act as a pure resistive load to the AC input line voltage. The degree to which the circuit matches a pure resistor is measured by the phase shift between the input voltage and input current and how well the shape of the input current waveform matches the shape of the sinusoidal input voltage. The cosine of the phase angle between the input voltage and input current is defined as the power factor (PF), and how well the shape of the input current waveform matches the shape of the input voltage is determined by the total harmonic distortion (THD). A power factor of 1.0 (maximum) corresponds to zero phase shift and a THD of 0% represents a pure sinewave (no distortion). For this reason it is desirable to have a high PF and a low THD. To achieve this, the IRS2166D includes an active power factor correction (PFC) circuit which, for an AC line input voltage, produces an AC line input current. The control method implemented in the IRS2166D is for a boost-type converter (Fig. 6) running in critical-conduction mode (CCM). This means that during each switching cycle of the PFC MOSFET, the circuit waits until the inductor current discharges to zero before turning the PFC MOSFET on again. The PFC MOSFET is turned on and off at a much higher frequency (>10 kHz) than the line input frequency (50 Hz to 60 Hz). CBUS + (+) (-) MPFC LPFC DPFC DC Bus Fig. 6: Boost-type PFC circuit LO CS 50 Pulses Preheat or Ignition Mode Fault Mode 2.0V Fig. 5: CS & LO Waveforms When the switch MPFC is turned on, the inductor LPFC is connected between the rectified line input (+) and (-) causing the current in LPFC to charge up linearly. When MPFC is turned off, LPFC is connected between the rectified line input (+) and the DC bus capacitor CBUS (through diode D PFC) and the stored current in L PFC flows into CBUS. As MPFC is turned on and off at a high-frequency, the voltage on CBUS charges up to a specified voltage. The feedback loop of the IRS2166D regulates this voltage to a fixed value by continuously monitoring the DC voltage and adjusting the on-time of MPFC accordingly. For an increasing DC bus the on-time is decreased, and for a decreasing DC bus the on-time is increased. This negative feedback control is performed with a slow loop speed and a low loop gain such that the average inductor current smoothly follows the low-frequency line input voltage for high power factor and low THD. The on-time of MPFC therefore appears to be fixed (with an additional modulation to be discussed later) over several cycles of the line voltage. With a fixed on-time, and an off-time determined by the inductor current discharging to zero, the result is a system where the switching frequency is free-running and constantly changing from a high frequency near the zero crossing of the AC input line voltage, to a lower frequency at the peaks (Fig. 7). V, I t Fig. 7: Sinusoidal line input voltage (solid line), triangular PFC inductor current and smoothed sinusoidal line input current (dashed line) over one half-cycle of the line input voltage When the line input voltage is low (near the zero crossing), the inductor current will charge up to a small amount and the discharge time will be fast resulting in a high switching frequency. When the input line voltage is high (near the peak), the inductor current will charge up to a higher amount and the discharge time will be longer giving a lower switching frequency. The triangular PFC inductor current is then smoothed by the EMI filter to produce a sinusoidal line input current. |
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