2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT723631/723641/723651 CMOS SyncFIFO™

512 x 36, 1,024 x 36 and 2,048 x 36

TQFP (PNG120, ORDER CODE: PF)

TOP VIEW

NOTE:

1. NC – No Connection

DESCRIPTION (CONTINUED)

PIN CONFIGURATION

B35

B34

B33

B32

GND

B31

B30

B29

B28

B27

B26

VCC

B25

B24

GND

B23

B22

B21

B20

B19

B18

GND

B17

B16

VCC

B15

B14

B13

B12

GND

A35

A34

A33

A32

VCC

A31

A30

GND

A29

A28

A27

A26

A25

A24

A23

GND

A22

VCC

A21

A20

A19

A18

GND

A17

A16

A15

A14

A13

VCC

A12

3023 drw03

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

devices may be used in parallel to create wider data paths. Expansion is

also possible in word depth.

These devices are a clocked FIFO, which means each port employs a

synchronous interface. All data transfers through a port are gated to the

LOW-to-HIGH transition of a continuous (free-running) port clock by en-

able signals. The continuous clocks for each port are independent of one

another and can be asynchronous or coincident. The enables for each

port are arranged to provide a simple interface between microprocessors

and/or buses with synchronous control.

The Input Ready (IR) flag and Almost-Full (AF) flag of the FIFO are

two-stage synchronized to CLKA. The Output Ready (OR) flag and Al-

most-Empty (AE) flag of the FIFO are two-stage synchronized to CLKB.

Offset values for the Almost-Full and Almost-Empty flags of the FIFO can be

programmed from port A or through a serial input.