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IDT723631 Datasheet(PDF) 9 Page - Renesas Technology Corp |
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IDT723631 Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 21 page COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 9 when CLKA and CLKB operate asynchronously to one another. OR and AE are synchronized to CLKB. IR and AF are synchronized to CLKA. Table 4 shows the relationship of each flag to the number of words stored in memory. OUTPUT READY FLAG (OR) The Output Ready flag of a FIFO is synchronized to the port Clock that reads data from its array (CLKB). When the OR flag is HIGH, new data is present in the FIFO output register. When the OR flag is LOW, the previ- ous data word is present in the FIFO output register and attempted FIFO reads are ignored. A FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an OR flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2. From the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of CLKB. Therefore, an OR flag is LOW if a word in memory is the next data to be sent to the FIFO output register and three CLKB cycles have not elapsed since the time the word was written. The OR flag of the FIFO remains LOW until the third LOW-to-HIGH transition of CLKB occurs, simultaneously forcing the OR flag HIGH and shifting the word to the FIFO output register. A LOW-to-HIGH transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent CLKB cycle may be the first synchroniza- tion cycle (see Figure 7). INPUT READY FLAG (IR) The Input Ready flag of a FIFO is synchronized to the port Clock that writes data to its array (CLKA). When the IR flag is HIGH, a memory location is free in the SRAM to write new data. No memory locations are free when the IR flag is LOW and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an IR flag monitors a write-pointer and read pointer comparator that indicates when the FIFO SRAM status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready to be written in a minimum of three cycles of CLKA. Therefore, an IR flag is LOW if less than two cycles of CLKA have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on CLKA after the read sets the Input Ready flag HIGH, and data can be written in the following cycle. A LOW-to-HIGH transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent CLKA cycle may be the first synchroniza- tion cycle (see Figure 8). ALMOST-EMPTY FLAG (AE) The Almost-Empty flag of a FIFO is synchronized to the port Clock that reads data from its array (CLKB). The state machine that controls an AE flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost-empty, almost-empty+1, or almost- empty+2. The almost-empty state is defined by the contents of register X. This register is loaded with a preset value during a FIFO reset, pro- TABLE 3 — PORT-B ENABLE FUNCTION TABLE CSB W/RB ENB MBB CLKB B0-A35 Outputs Port Functions H XXXX In High-Impedance State None L L L X X In High-Impedance State None LL H L ↑ In High-Impedance State None LL H H ↑ In High-Impedance State Mail2 Write L H L L X Active, FIFO Output Register None LH H L ↑ Active, FIFO Output Register FIFO read L H L H X Active, Mail1 Register None L HHH ↑ Active, Mail1 Register Mail1 Read (Set MBF1 HIGH) TABLE 2 — PORT-A ENABLE FUNCTION TABLE CSA W/RA ENA MBA CLKA A0-A35 Outputs Port Functions H XXXX In High-Impedance State None L H L X X In High-Impedance State None LH H L ↑ In High-Impedance State FIFO Write L HHH ↑ In High-Impedance State Mail1 Write LLLL X Active, Mail2 Register None LL H L ↑ Active, Mail2 Register None L L L H X Active, Mail2 Register None LL H H ↑ Active, Mail2 Register Mail2 Read (Set MBF2 HIGH) |
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