6

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT723631/723641/723651 CMOS SyncFIFO™

512 x 36, 1,024 x 36 and 2,048 x 36

AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF

SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

(Commercial: VCC = 5.0V ± 10%, TA = 0

°C to +70°C

Commercial

IDT723631L15

IDT723641L15

IDT723651L15

Symbol

Parameter

Min.

Max.

Unit

fS

Clock Frequency, CLKA or CLKB

–

66.7

MHz

tCLK

Clock Cycle Time, CLKA or CLKB

15

–

ns

tCLKH

Pulse Duration, CLKA or CLKB HIGH

6

–

ns

tCLKL

Pulse Duration, CLKA or CLKB LOW

6

–

ns

tDS

Setup Time, A0-A35 before CLKA

↑and B0-B35 before CLKB↑

5–

ns

tENS1

Setup Time, ENA to CLKA

↑; ENB to CLKB↑

5–

ns

tENS2

Setup Time, CSA, W/RA, and MBA to CLKA

↑; CSB, W/RB and MBB to CLKB↑

7–

ns

tRMS

Setup Time, RTM and RFM to CLKB

↑

6–

ns

tRSTS

Setup Time, RST LOW before CLKA

↑ or CLKB↑(1)

5–

ns

tFSS

Setup Time, FS0 and FS1 before RST HIGH

9

–

ns

tSDS(2)

Setup Time, FS0/SD before CLKA

↑

5–

ns

tSENS(2)

Setup Time, FS1/SEN before CLKA

↑

5–

ns

tDH

Hold Time, A0-A35 after CLKA

↑ and B0-B35 after CLKB↑

0–

ns

tENH1

Hold Time, ENA after CLKA

↑; ENB after CLKB↑

0–

ns

tENH2

Hold Time, CSA, W/RA, and MBA after CLKA

↑; CSB, W/RB and MBB after CLKB↑

0–

ns

tRMH

Hold Time, RTM and RFM after CLKB

↑

0–

ns

tRSTH

Hold Time, RST LOW after CLKA

↑ or CLKB↑(1)

5–

ns

tFSH

Hold Time, FS0 and FS1 after RST HIGH

0

–

ns

tSPH(2)

Hold Time, FS1/SEN HIGH after RST HIGH

0

–

ns

tSDH(2)

Hold Time, FS0/SD after CLKA

↑

0–

ns

tSENH(2)

Hold Time, FS1/SEN after CLKA

↑

0–

ns

tSKEW1(3)

Skew Time, between CLKA

↑ and CLKB↑ for OR and IR

9

–

ns

tSKEW2(3)

Skew Time, between CLKA

↑and CLKB↑ for AE and AF

12

–

ns

NOTES:

1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

2. Only applies when serial load method is used to program flag Offset registers.

3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

4. Design simulated but not tested (typical values).