COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT723631/723641/723651 CMOS SyncFIFO™

512 x 36, 1,024 x 36 and 2,048 x 36

5

Figure 1. Typical Characteristics: Supply vs Clock Frequency

CALCULATING POWER DISSIPATION

The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723641 with CLKA and CLKB set

to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to

normalize the graph to a zero-capacitance load. Once the capacitance load per data-output channel and the number of IDT723631/723641/723651

inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.

With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:

PT = VCC x [ICC(f) + (N x

ΔICC x dc)] + Σ(CL x VCC2 x fO)

where:

N

= number of inputs driven by TTL levels

ΔICC = increase in power supply current for each input at a TTL HIGH level

dc

= duty cycle of inputs at a TTL HIGH level of 3.4

CL

= output capacitance load

fO

= switching frequency of an output

When no reads or writes are occurring on these devices, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is

calculated by:

PT = VCC x fS x 0.209 mA/MHz

010

20

30

40

50

60

70

0

50

100

150

200

250

VCC = 5.0V

fS

⎯ Clock Frequency ⎯ MHz

VCC= 4.5V

VCC = 5.5V

3023 drw04

fdata = 1/2 fS

TA = 25

°C

CL = 0pF