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IDT723631 Datasheet(PDF) 3 Page - Renesas Technology Corp

Part # IDT723631
Description  CMOS SyncFIFO™512 x 36 1,024 x 36 2,048 x 36
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

IDT723631 Datasheet(HTML) 3 Page - Renesas Technology Corp

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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
3
PIN DESCRIPTION
Symbol
Name
I/O
Description
A0-A35
Port-AData
I/O
36-bitbidirectionaldataportforsideA.
AE
Almost-Empty
O
Programmable flag synchronized to CLKB. It is LOW when the number of words in the FIFO is less than or equal to the value in
Flag
theAlmost-Emptyregister(X).
AF
Almost-Full
O
Programmable flag synchronized to CLKA. It is LOW when the number of empty locations in FIFO is less than or equal to the
Flag
valueintheAlmost-FullOffsetregister(Y).
B0-B35
Port-BData
I/O
36-bitbidirectionaldataportforsideB.
CLKA
Port-A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through port-A and may be asynchronous or coincident to CLKB.
IR and AF are synchronous to the LOW-to-HIGH transition of CLKA.
CLKB
Port-B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through port-B and may be asynchronous or coincident to CLKA.
OR and AE are synchronous to the LOW-to-HIGH transition of CLKB.
CSA
Port-A Chip
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. The A0-A35 outputs are in the
Select
high-impedance state when CSA is HIGH.
CSB
Port-B Chip
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. The B0-B35 outputs are in the
Select
high-impedance state when CSB is HIGH.
ENA
Port-AEnable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
ENB
Port-BEnable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
FS1/
Flag-Offset
I
FS1/SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During a device reset, FS1/SENand
SEN,
Select 1/
FS0/SDselectstheflagoffsetprogrammingmethod.ThreeOffsetregisterprogrammingmethodsareavailable:automatically
SerialEnable
load one of two preset values, parallel load from port A, and serial load.
FS0/SD
FlagOffset0/
WhenserialloadisselectedforflagOffsetregisterprogramming,FS1/SENis used as an enable synchronous to the LOW-to-
SerialData
HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on FS0/SD into the X and Y
registers.ThenumberofbitwritesrequiredtoprogramtheOffsetregistersis18/20/22.ThefirstbitwritestorestheY-register
MSB and the last bit write stores the X-register LSB.
IR
InputReady
O
IR is synchronized to the LOW-to-HIGH transition of CLKA. When IR is LOW, the FIFO is full and writes to its array are
Flag
disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point of the retransmit
dataandpreventsfurtherwrites. IR is set LOW during reset and is set HIGH after reset.
MBA
Port-A Mailbox
I
A HIGH level chooses a mailbox register for a port-A read or write operation.
Select
MBB
Port-B Mailbox
I
A HIGH level chooses a mailbox register for a port-B read or write operation. When the B0-B35 outputs are active, a HIGH
Select
level on MBB selects data from the mail1 register for output and a LOW level selects FIFO data for output.
MBF1
Mail1Register
O
MBF1 is set LOW by the LOW-to-HIGH transition of CLKA that writes data to the mail1 register. MBF1 is set HIGH by a
Flag
LOW-to-HIGH transition of CLKB when a port-B readis selected and MBB is HIGH. MBF1 is set HIGH by a reset.
MBF2
Mail2Register
O
MBF2 is set LOW by the LOW-to-HIGH transition of CLKB that writes data to the mail2 register. MBF2 is set HIGH by a
Flag
LOW-to-HIGH transition of CLKA when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH by a reset.
OR
OutputReady
O
OR is synchronized to the LOW-to-HIGH transition of CLKB. When OR is LOW, the FIFO is empty and reads are disabled.
Flag
Ready data is present in the output register of the FIFO when OR is HIGH. OR is forced LOW during the reset and goes
HIGH on the third LOW-to-HIGH transition of CLKB after a word is loaded to empty memory.
RFM
ReadFrom
I
When the FIFO is in retransmit mode, a HIGH on RFM enables a LOW-to-HIGH transition of CLKB to reset the read pointer
Mark
tothebeginningretransmitlocationandoutputthefirstselectedretransmitdata.
RST
Reset
I
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST
is LOW. The LOW-to-HIGH transition of RST latches the status of FS0 and FS1 for AF and AE offset selection.
RTM
Retransmit
I
When RTM is HIGH and valid data is present in the FIFO output register (OR is HIGH), a LOW-to-HIGH transition of CLKB
Mode
selectsthedataforthebeginningofaretransmitandputstheFIFOinretransmitmode.Theselectedwordremainstheinitial
retransmit point until a LOW- to-HIGH transition of CLKB occurs while RTM is LOW, taking the FIFO out of retransmit mode.
W/RA
Port-AWrite/
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The
ReadSelect
A0-A35 outputs are in the high-impedance state when W/RA is HIGH.
W/RB
Port-BWrite/
I
A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The
ReadSelect
B0-B35 outputs are in the high-impedance state when W/RB is LOW.


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