Cmod A7 Reference Manual

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Page 4 of 10

2

FPGA Configuration

After power-on, the Artix-7 FPGA must be configured (or programmed) before it can perform any functions. Users

can configure the FPGA in one of two ways:

1.

A PC can use the Digilent USB-JTAG circuitry to program the FPGA any time the power is on.

2.

A file stored in the nonvolatile serial (Quad-SPI) flash device can be transferred to the FPGA using the SPI

port.

On power-up, the Cmod A7 is programmed by the Quad-SPI flash. If the FPGA does not find a valid configuration

file in the flash, then it will remain unconfigured until it is programmed over JTAG.

The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The Vivado

software from Xilinx can create bitstreams from VHDL or Verilog-based source files.

Bitstreams are stored in volatile memory cells within the FPGA. This data defines the FPGA’s logic functions and

circuit connections, and it remains valid until it is erased by removing board power, by pressing the reset button

attached to the PROG input, or by writing a new configuration file using the JTAG port.

Both the Artix-7 35T and 15T bitstreams are typically 17,536,096 bits. The time it takes to program the Cmod A7

can be decreased by compressing the bitstream before programming and then allowing the FPGA to decompress

the bitstream itself during configuration. Depending on design complexity, compression ratios of 10x can be

achieved. Bitstream compression can be enabled within the Vivado tools to occur during generation. For

instructions on how to do this, consult the Xilinx documentation for Vivado.

After being successfully programmed, the FPGA will cause the “DONE” LED to illuminate.

The following sections provide greater detail about programming the Cmod A7 using the different methods

available.

2.1

JTAG Configuration

The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture,

commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using

the onboard Digilent USB-JTAG circuitry (Micro-USB port). Users can perform JTAG programming any time after the

Cmod A7 has been powered on. If the FPGA is already configured, then the existing configuration is overwritten

with the bitstream being transmitted over JTAG.

Programming the Cmod A7 with an uncompressed bitstream using the on-board USB-JTAG circuitry usually takes

around 6 seconds. JTAG programming can be done using the hardware manager in Vivado.

Warning: When a USB host is attached to the Micro-USB connector, the VU pin on the DIP connector (pin 24) is

driven to the voltage being provided by the USB host (typically between 4.5V-5.5V). If you have a power source

attached to the VU pin, you must disconnect it before attaching a USB host, or risk damaging it. This can be

particularly dangerous if the power source is a battery.

2.2

Quad-SPI Configuration

Since the FPGA's memory on the Cmod A7 is volatile, it relies on the Quad-SPI flash memory to store the

configuration between power cycles. This configuration mode is referred to in Xilinx documentation as Master SPI.

The blank FPGA takes the role of master and reads the configuration file out of the flash device upon power-up. To

that effect, a configuration file needs to be downloaded first to the flash. When programming a nonvolatile flash