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AN1523 Datasheet(PDF) 8 Page - STMicroelectronics |
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AN1523 Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 24 page ![]() AN1523 APPLICATION NOTE 8/24 Dynamic Load Tests The pictures 11 and 12 show the output voltage regulation against a dynamic load variation of +5V output, at the nominal mains voltage values. As shown in the pictures, the voltage variation is always better than 1% and the response is fast, within 2 ms. This allows to power µP or any logic circuitry without the risk of inopportune reset or logic malfunctioning. Even the 12V variation is good, remaining within its tolerance with still margin. Start-Up Behaviours @full load In figure 13 and 14 there are the rising slopes at full load of the output voltages at nominal input mains voltages. As shown in the pictures, the rising time at 220Vac is a bit faster than at 115Vac, however they are similar. The rising slopes are always monotonic overall the input mains range. This characteristic is quite important power- ing a µP and its peripherals as in this case, thus avoiding problem at start-up for the equipment. In figure 15, there are the same waveforms captured during the start-up in stand-by. Even in this case, the be- haviour of the circuit is always correct overall the input mains range. A slight overshoot is present in all conditions but it is negligible because the voltage remains always under con- trol and the variation is within the tolerances. Load condition: +12V: FULL LOAD +5V: L O AD 50% ÷ 100%, 12H z Figure 11. DYNAMIC LOAD TEST Figure 12. DYNAMIC LOAD TEST Vin = 115 Vrms - 50 Hz @FULL LOAD Vin = 220 Vrms - 50 Hz @FULL LOAD CH1: VC1+ CH1: VC1+ CH3: +5VOUT CH3: +5VOUT CH4: +5IOUT CH4: +5IOUT |
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