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AN1523 Datasheet(PDF) 7 Page - STMicroelectronics |
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AN1523 Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 24 page 7/24 AN1523 APPLICATION NOTE decrease the switching losses during light load operation, thus improving the stand-by efficiency. For reference, also the Vcomp and the Vcc are captured. In detail, the Vcc shows that there is still margin when working at light load respect to the Vccoff value (which is 6.5V typ. and 7Vmax.). This guarantees that even with a different transformer batch, delivering may be a bit lower Vcc, the converter will still work correctly, without showing any irregular behaviour at start-up or inopportune missing start-up due to a Vcc too low, unable to power correctly the primary controller. Output voltage ripple @full load In Figure 9 the output voltage ripple at switching frequency have been measured. As per the previous measures, the probes have been connected on test points after the output connector. The ripple and the spikes are very low making this design suitable to power sensitive loads. In Figure 10, the residual ripple on the output voltages at mains frequency is measured. The low frequency residual ripple compared with the 100Hz undulation across C1 (input Elcap), demonstrates an excellent rejection of the circuit (~66dB) at 115V. Obviously the low frequen- cy rejection becomes even higher when the circuit is working at 220Vac (figure 10). At that voltage, the rejection becomes 76dB and this means a residual line ripple on the 5V output of 3mV only. Figure 9. HF RIPPLE Figure 10. LINE RIPPLE REJECTION Vin = 115 Vrms - 50 Hz @FULL LOAD Vin = 115 Vrms - 50 Hz @FULL LOAD REF1: VRIPPLE +5V CH1: VC1+ CH3: VRIPPLE +12V CH2: +12VOUT CH3: +5VOUT |
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