89H32H8G2ZCBL datasheet(2/41 Pages) RENESAS

Part #	89H32H8G2ZCBL

Description	32-Lane 8-Port PCIe® Gen2 System Interconnect Switch

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Manufacturer	RENESAS [Renesas Technology Corp]

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November 28, 2011

IDT 89HPES32H8G2 Data Sheet

–

Configurable presence detect supports card and cable appli-

cations

–

GPE output pin for hot-plug event notification

• Enables SCI/SMI generation for legacy operating system

support

–

Hot-swap capable I/O

 Power Management

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Supports D0, D3hot and D3 power management states

–

Active State Power Management (ASPM)

• Supports L0, L0s, L1, L2/L3 Ready and L3 link states

• Configurable L0s and L1 entry timers allow performance/

power-savings tuning

–

Supports PCI Express Power Budgeting Capability

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SerDes power savings

• Supports low swing / half-swing SerDes operation

• SerDes optionally turned-off in D3hot

• SerDes associated with unused ports are turned-off

• SerDes associated with unused lanes are placed in a low

power state

 9 General Purpose I/O

 Reliability, Availability and Serviceability (RAS)

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ECRC support

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AER on all ports

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SECDED ECC protection on all internal RAMs

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End-to-end data path parity protection

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Checksum Serial EEPROM content protected

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Autonomous link reliability (preserves system operation in the

presence of faulty links)

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Ability to generate an interrupt (INTx or MSI) on link up/down

transitions

 Test and Debug

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On-chip link activity and status outputs available for Port 0

(upstream port)

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Per port link activity and status outputs available using

external I2C I/O expander for all other ports

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SerDes test modes

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Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG

 Power Supplies

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Requires only two power supply voltages (1.0 V and 2.5 V)

Note that a 3.3V is preferred for VDDI/O

–

No power sequencing requirements

 Packaged in a 23mm x 23mm 484-ball Flip Chip BGA with

1mm ball spacing

Product Description

Utilizing standard PCI Express interconnect, the PES32H8G2

provides the most efficient fan-out solution for applications requiring

high throughput, low latency, and simple board layout with a minimum

number of board layers. It provides 32 GBps (256 Gbps) of aggregated,

full-duplex switching capacity through 32 integrated serial lanes, using

proven and robust IDT technology. Each lane provides 5 GT/s of band-

width in both directions and is fully compliant with PCI Express Base

Specification, Revision 2.0.

The PES32H8G2 is based on a flexible and efficient layered archi-

tecture. The PCI Express layer consists of SerDes, Physical, Data Link

and Transaction layers in compliance with PCI Express Base specifica-

tion Revision 2.0. The PES32H8G2 can operate either as a store and

forward or cut-through switch. It supports eight Traffic Classes (TCs)

and one Virtual Channel (VC) with sophisticated resource management

to enable efficient switching and I/O connectivity for servers, storage,

and embedded processors with limited connectivity.

The PES32H8G2 is a partitionable PCIe switch. This means that in

addition to operating as a standard PCI express switch, the

PES32H8G2 ports may be partitioned into groups that logically operate

as completely independent PCIe switches. Figure 2 illustrates a three

partition PES32H8G2 configuration.

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