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November 28, 2011

IDT 89HPES32H8G2 Data Sheet

Figure 5 JTAG AC Timing Waveform

Signal

Symbol

Reference

Edge

Min

Max

Unit

Timing

Diagram

Reference

JTAG

JTAG_TCK

Tper_16a

none

50.0

—

ns

See Figure 5.

Thigh_16a,

Tlow_16a

10.0

25.0

ns

JTAG_TMS1,

JTAG_TDI

1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N

changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK

when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.

Tsu_16b

JTAG_TCK rising

2.4

—

ns

Thld_16b

1.0

—

ns

JTAG_TDO

Tdo_16c

JTAG_TCK falling

—

20

ns

Tdz_16c2

2. The values for this symbol were determined by calculation, not by testing.

—20

ns

JTAG_TRST_N

Tpw_16d2

none

25.0

—

ns

Table 12 JTAG AC Timing Characteristics

Tpw_16d

Tdz_16c

Tdo_16c

Thld_16b

Tsu_16b

Thld_16b

Tsu_16b

Tlow_16a

Tlow_16a

Tper_16a

Thigh_16a

JTAG_TCK

JTAG_TDI

JTAG_TMS

JTAG_TDO

JTAG_TRST_N