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89H32H8G2ZCBL Datasheet(PDF) 1 Page - Renesas Technology Corp |
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89H32H8G2ZCBL Datasheet(HTML) 1 Page - Renesas Technology Corp |
1 / 41 page 1 of 40 November 28, 2011 ® IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. Device Overview The 89HPES32H8G2 is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES32H8G2 is a 32-lane, 8-port system interconnect switch optimized for PCI Express Gen2 packet switching in high-performance applications, supporting multiple simulta- neous peer-to-peer traffic flows. Target applications include servers, storage, communications, embedded systems, and multi-host or intelli- gent I/O based systems with inter-domain communication. Features High Performance Non-Blocking Switch Architecture – 32-lane 8-port PCIe switch • Four x8 switch ports each of which can bifurcate to two x4 ports (total of eight x4 ports) – Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s Gen1 operation – Delivers up to 32 GBps (256 Gbps) of switching capacity – Supports 128 Bytes to 2 KB maximum payload size – Low latency cut-through architecture – Supports one virtual channel and eight traffic classes Standards and Compatibility – PCI Express Base Specification 2.0 compliant – Implements the following optional PCI Express features • Advanced Error Reporting (AER) on all ports • End-to-End CRC (ECRC) • Access Control Services (ACS) • Power Budgeting Enhanced Capability • Device Serial Number Enhanced Capability • Sub-System ID and Sub-System Vendor ID Capability • Internal Error Reporting ECN • Multicast ECN • VGA and ISA enable • L0s and L1 ASPM •ARI ECN Port Configurability – x4 and x8 ports • Ability to merge adjacent x4 ports to create a x8 port – Automatic per port link width negotiation (x8 → x4 → x2 → x1) – Crosslink support – Automatic lane reversal – Autonomous and software managed link width and speed control – Per lane SerDes configuration • De-emphasis • Receive equalization • Drive strength Switch Partitioning – IDT proprietary feature that creates logically independent switches in the device – Supports up to 8 fully independent switch partitions – Configurable downstream port device numbering – Supports dynamic reconfiguration of switch partitions • Dynamic port reconfiguration (downstream, and upstream) • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions Initialization / Configuration – Supports Root (BIOS, OS, or driver), Serial EEPROM, or SMBus switch initialization – Common switch configurations are supported with pin strap- ping (no external components) – Supports in-system Serial EEPROM initialization/program- ming Quality of Service (QoS) – Port arbitration • Round robin – Request metering • IDT proprietary feature that balances bandwidth among switch ports for maximum system throughput – High performance switch core architecture • Combined Input Output Queued (CIOQ) switch architecture with large buffers Multicast – Compliant to the PCI-SIG multicast ECN – Supports arbitrary multicasting of Posted transactions – Supports 64 multicast groups – Multicast overlay mechanism support – ECRC regeneration support Clocking – Supports 100 MHz and 125 MHz reference clock frequencies – Flexible port clocking modes • Common clock • Non-common clock • Local port clock with SSC and port reference clock input Hot-Plug and Hot Swap – Hot-plug controller on all ports • Hot-plug supported on all downstream switch ports – All ports support hot-plug using low-cost external I2C I/O expanders 89HPES32H8G2 Data Sheet 32-Lane 8-Port PCIe® Gen2 System Interconnect Switch |
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