89H32H8G2ZCBL datasheet(8/41 Pages) RENESAS

Part #	89H32H8G2ZCBL

Description	32-Lane 8-Port PCIe® Gen2 System Interconnect Switch

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Manufacturer	RENESAS [Renesas Technology Corp]

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November 28, 2011

IDT 89HPES32H8G2 Data Sheet

P45MERGEN

I

Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled low

internally. When this pin is low, port 4 is merged with port 5 to form a single

x8 port. The Serdes lanes associated with port 5 become lanes 4 through 7

of port 4. When this pin is high, port 4 and port 5 are not merged, and each

operates as a single x4 port.

P67MERGEN

I

Port 6 and 7 Merge. P67MERGEN is an active low signal. It is pulled low

internally. When this pin is low, port 6 is merged with port 7 to form a single

x8 port. The Serdes lanes associated with port 7 become lanes 4 through 7

of port 6. When this pin is high, port 6 and port 7 are not merged, and each

operates as a single x4 port.

PERSTN

I

Global Reset. Assertion of this signal resets all logic inside PES32H8G2.

RSTHALT

I

Reset Halt. When this signal is asserted during a PCI Express fundamental

reset, PES32H8G2 executes the reset procedure and remains in a reset

state with the Master and Slave SMBuses active. This allows software to

read and write registers internal to the device before normal device opera-

tion begins. The device exits the reset state when the RSTHALT bit is

cleared in the SWCTL register by an SMBus master.

SWMODE[3:0]

I

Switch Mode. These configuration pins determine the PES32H8G2 switch

operating mode. Note: These pins should be static and not change follow-

ing the negation of PERSTN.

0x0 - Single partition

0x1 - Single partition with Serial EEPROM initialization

0x2 through 0x7 - Reserved

0x8 - Single partition with port 0 selected as the upstream port (port 2 dis-

abled)

0x9 - Single partition with port 2 selected as the upstream port (port 0 dis-

abled)

0xA - Single partition with Serial EEPROM initialization and port 0 selected

as the upstream port (port 2 disabled)

0xB - Single partition with Serial EEPROM initialization and port 2 selected

as the upstream port (port 0 disabled)

0xC - Multi-partition

0xD - Multi-partition with Serial EEPROM initialization

0xE - Reserved

0xF - Reserved

Signal

Type

Name/Description

JTAG_TCK

I

JTAG Clock. This is an input test clock used to clock the shifting of data

into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is

independent of the system clock with a nominal 50% duty cycle.

JTAG_TDI

I

JTAG Data Input. This is the serial data input to the boundary scan logic or

JTAG Controller.

Table 6 Test Pins (Part 1 of 2)

Signal

Type

Name/Description

Table 5 System Pins (Part 2 of 2)

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