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89H32H8G2ZCBL Datasheet(PDF) 4 Page - Renesas Technology Corp

Part # 89H32H8G2ZCBL
Description  32-Lane 8-Port PCIe® Gen2 System Interconnect Switch
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

89H32H8G2ZCBL Datasheet(HTML) 4 Page - Renesas Technology Corp

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November 28, 2011
IDT 89HPES32H8G2 Data Sheet
Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin. In addition, the slave SMBus has SSMBADDR1 and
SSMBADDR2 pins. As shown in Figure 3, the master and slave SMBuses may only be used in a split configuration.
Figure 3 Split SMBus Interface Configuration
The switch’s SMBus master interface does not support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the
SMBus lines that connect to the serial EEPROM and I/O expander slaves. In the split configuration, the master and slave SMBuses operate as two
independent buses; thus, multi-master arbitration is not required.
Hot-Plug Interface
The PES32H8G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the
PES32H8G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and
configuration, whenever the state of a Hot-Plug output needs to be modified, the PES32H8G2 generates an SMBus transaction to the I/O expander
with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEX-
PINTN input pin (alternate function of GPIO) of the PES32H8G2. In response to an I/O expander interrupt, the PES32H8G2 generates an SMBus
transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES32H8G2 provides 9 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Processor
Switch
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
...
Hot-Plug
I/O
Expander


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