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November 28, 2011

IDT 89HPES32H8G2 Data Sheet

Block Diagram

I

Figure 1 Internal Block Diagram

Figure 2 Example of Usage of Switch Partitioning

SMBus Interface

The PES32H8G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES32H8G2,

allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration

register values of the PES32H8G2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is

also used by an external Hot-Plug I/O expander.

8-Port Switch Core / 32 Gen2 PCI Express Lanes

Frame Buffer

Route Table

Port

Arbitration

Scheduler

SerDes

Phy

Logical

Layer

SerDes

Phy

Logical

Layer

SerDes

Phy

Logical

Layer

Multiplexer / Demultiplexer

Transaction Layer

Data Link Layer

SerDes

Phy

Logical

Layer

SerDes

Phy

Logical

Layer

SerDes

Phy

Logical

Layer

SerDes

Phy

Logical

Layer

Multiplexer / Demultiplexer

Transaction Layer

Data Link Layer

SerDes

Phy

Logical

Layer

SerDes

Phy

Logical

Layer

SerDes

Phy

Logical

Layer

SerDes

Phy

Logical

Layer

Multiplexer / Demultiplexer

Transaction Layer

Data Link Layer

SerDes

Phy

Logical

Layer

(Port 0)

(Port 1)

(Port 7)

Partition 1 – Virtual PCI Bus

P2P

Bridge

Partition 1

Upstream Port

P2P

Bridge

P2P

Bridge

P2P

Bridge

P2P

Bridge

Partition 2 – Virtual PCI Bus

P2P

Bridge

P2P

Bridge

P2P

Bridge

Partition 3 – Virtual PCI Bus

P2P

Bridge

P2P

Bridge

P2P

Bridge

Partition 1

Downstream Ports

Partition 2

Downstream Ports

Partition 3

Downstream Ports

Partition 2

Upstream Port

Partition 3

Upstream Port