Register description

LIS302DL

26/29

7.15

FF_WU_SRC_2 (35h)

Free-fall and wake-up source register. Read only register.

Reading at this address clears FF_WU_SRC_2 register and the FF, WU 2 interrupt and

allows the refreshment of data in the FF_WU_SRC_2 register if the latched option was

chosen.

7.16

FF_WU_THS_2 (36h)

Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If

DCRM=0 counter is resetted when the interrupt is no more active else if DCRM=1 duration

counter is decremented.

7.17

FF_WU_DURATION_2 (37h)

Duration register for Free-Fall/Wake-Up interrupt 2. Duration step and maximum value

depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400Hz, else step

10 msec, from 0 to 2.55 sec when ODR=100Hz. The counter used to implement duration

function is blocked when LIR=1 in configuration register and the interrupt event is verified.

X

IA

ZH

ZL

YHYLXHXL

IA

Interrupt Active. Default value: 0

(0: no interrupt has been generated;

1: one or more interrupt event has been generated)

ZH

Z High. Default value: 0

(0: no interrupt; 1: ZH event has occurred)

ZL

Z Low. Default value: 0

(0: no interrupt; 1: ZL event has occurred)

YH

Y High. Default value: 0

(0: no interrupt; 1: YH event has occurred)

YL

Y Low. Default value: 0

(0: no interrupt; 1: YL event has occurred)

XH

X High. Default value: 0

(0: no interrupt; 1: XH event has occurred)

XL

X Low. Default value: 0

(0: no interrupt; 1: XL event has occurred)

DCRM

THS6

THS5

THS4

THS3

THS2

THS1

THS0

DCRM

Resetting mode selection. Default value: 0

(0: counter resetted; 1: counter decremented)

THS6, THS0

Free-fall / wake-up Threshold. Default value: 000 0000

D7

D6

D5

D4

D3

D2

D1

D0

D7-D0

Duration value. Default value: 0000 0000