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MC68HC912BL16 Datasheet(PDF) 100 Page - NXP Semiconductors |
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MC68HC912BL16 Datasheet(HTML) 100 Page - NXP Semiconductors |
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100 / 128 page  MC68HC912BL16 100 MC68HC912BL16TS/D time of the error. Automatically cleared by a read of the SP0SR (with WCOL set) followed by an access (read or write) to the SP0DR register. 0 = No write collision 1 = Indicates that a serial transfer was in progress when the MCU tried to write new data into the SP0DR data register. MODF — SPI Mode Error Interrupt Status Flag This bit is set automatically by SPI hardware if the MSTR control bit is set and the slave select input pin becomes zero. This condition is not permitted in normal operation. In the case where DDRS bit 7 is set, the PS7 pin is a general-purpose output pin or SS output pin rather than being dedicated as the SS input for the SPI system. In this special case the mode fault function is inhibited and MODF remains cleared. This flag is automatically cleared by a read of the SP0SR (with MODF set) followed by a write to the SP0CR1 register. Read anytime (normally only after SPIF flag set). Write anytime (see WCOL write collision flag). Reset does not affect this address. This 8-bit register is both the input and output register for SPI data. Reads of this register are double buffered but writes cause data to be written directly into the serial shifter. In the SPI system the 8-bit data register in the master and the 8-bit data register in the slave are linked by the MOSI and MISO wires to form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit reg- ister is serially shifted eight bit positions by the SCK clock from the master so the data is effectively ex- changed between the master and the slave. Note that some slave devices are very simple and either accept data from the master without returning data to the master or pass data to the master without re- quiring data from the master. 13.4 Port S In all modes, port S bits PS[7:4] and PS[1:0] can be used for either general-purpose I/O, or with the SCI and SPI subsystems. During reset, port S pins are configured as high-impedance inputs (DDRS is cleared). PORTS can be read anytime. When configured as an input, a read will return the pin level. When con- figured as output, a read will return the latched output data. Writes do not change pin state when pin configured for SPI or SCI output. After reset all bits are configured as general-purpose inputs. Port S shares function with the on-chip serial systems (SPI0 and SCI0). Read or write anytime. After reset, all general-purpose I/O are configured for input only. SP0DR — SPI Data Register $00D5 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 RESET: 0 0 0 0 0 0 0 0 PORTS — Port S Data Register $00D6 Bit 7 6 5 4 3 2 1 Bit 0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 Pin Function SS CS SCK MOSI MOMI MISO SISO N/A N/A TXD0 RXD0 DDRS — Data Direction Register for Port S $00D7 Bit 7 6 5 4 3 2 1 Bit 0 DDS7 DDS6 DDS5 DDS4 DDS3 DDS2 DDS1 DDS0 RESET: 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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