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MC68HC912BL16 Datasheet(PDF) 99 Page - NXP Semiconductors |
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MC68HC912BL16 Datasheet(HTML) 99 Page - NXP Semiconductors |
99 / 128 page MC68HC912BL16TS/D 99 Read anytime. Write anytime. At reset, E Clock divided by 2 is selected. SPR[2:0] — SPI Clock (SCK) Rate Select Bits These bits are used to specify the SPI clock rate. Read anytime. Write has no meaning or effect. SPIF — SPI Interrupt Request SPIF is set after the eighth SCK cycle in a data transfer and it is cleared by reading the SP0SR register (with SPIF set) followed by an access (read or write) to the SPI data register. WCOL — Write Collision Status Flag The MCU write is disabled to avoid writing over the data being transferred. No interrupt is generated because the error status flag can be read upon completion of the transfer that was in progress at the Pin Mode SPC01 NOTES: 1. The serial pin control 0 bit enables bidirectional configurations. MSTR MISO2 2. Slave output is enabled if DDS4 = 1, SS = 0 and MSTR = 0. (#1, #3) MOSI3 3. Master output is enabled if DDS5 = 1 and MSTR = 1. (#2, #4) SCK4 4. SCK output is enabled if DDS6 = 1 and MSTR = 1. (#2, #4) SS5 5. SS output is enabled if DDS7 = 1, SSOE = 1 and MSTR = 1. (#2, #4) #1 Normal 0 0 Slave Out Slave In SCK In SS In #2 1 Master In Master Out SCK Out SS I/O #3 Bidirectional 1 0 Slave I/O GPI/O SCK In SS In #4 1 GPI/O Master I/O SCK Out SS I/O SP0BR — SPI Baud Rate Register $00D2 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 SPR2 SPR1 SPR0 RESET: 0 0 0 0 0 0 0 0 Table 32 SPI Clock Rate Selection SPR2 SPR1 SPR0 E Clock Divisor Frequency at E Clock = 4 MHz Frequency at E Clock = 8 MHz 0 0 0 2 2.0 MHz 4.0 MHz 0 0 1 4 1.0 MHz 2.0 MHz 0 1 0 8 500 kHz 1.0 MHz 0 1 1 16 250 kHz 500 kHz 1 0 0 32 125 kHz 250 kHz 1 0 1 64 62.5 kHz 125 kHz 1 1 0 128 31.3 kHz 62.5 kHz 1 1 1 256 15.6 kHz 31.3 kHz SP0SR — SPI Status Register $00D3 Bit 7 6 5 4 3 2 1 Bit 0 SPIF WCOL 0 MODF 0 0 0 0 RESET: 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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