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MC68HC912BL16 Datasheet(PDF) 81 Page - NXP Semiconductors |
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MC68HC912BL16 Datasheet(HTML) 81 Page - NXP Semiconductors |
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81 / 128 page  MC68HC912BL16TS/D 81 Read or write anytime. NOTE Port T[6] is not bonded to any pin in MC68HC912BL16. EDGnB, EDGnA — Input Capture Edge Control These eight pairs of control bits configure the input capture edge detector circuits. The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the cor- responding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled to cause a hardware interrupt. Read or write anytime. NOTE Port T[6] is not bonded to any pin in MC68HC912BL16. C7I–C0I — Input Capture/Output Compare “x” Interrupt Enable. Read or write anytime. TOI — Timer Overflow Interrupt Enable 0 = Interrupt inhibited 1 = Hardware interrupt requested when TOF flag set PUPT — Timer Pull-Up Resistor Enable This enable bit controls pull-up resistors on the timer port pins when the pins are configured as inputs. 1 = Enable pull-up resistor function 0 = Disable pull-up resistor function RDPT — Timer Drive Reduction This bit reduces the effective output driver size which can reduce power supply current and generated noise depending upon pin loading. TCTL4 — Timer Control Register 4 $008B Bit 7 6 5 4 3 2 1 Bit 0 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A RESET: 0 0 0 0 0 0 0 0 Table 26 Edge Detector Circuit Configuration EDGnB EDGnA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge (rising or falling) TMSK1 — Timer Interrupt Mask 1 $008C Bit 7 6 5 4 3 2 1 Bit 0 C7I C6I C5I C4I C3I C2I C1I C0I RESET: 0 0 0 0 0 0 0 0 TMSK2 — Timer Interrupt Mask 2 $008D Bit 7 6 5 4 3 2 1 Bit 0 TOI 0 PUPT RDPT TCRE PR2 PR1 PR0 RESET: 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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