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MC68HC912BL16 Datasheet(PDF) 56 Page - NXP Semiconductors |
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MC68HC912BL16 Datasheet(HTML) 56 Page - NXP Semiconductors |
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56 / 128 page  MC68HC912BL16 56 MC68HC912BL16TS/D To give a maskable interrupt source highest priority, write the low byte of the vector address to the HPRIO register. For example, writing $F0 to HPRIO would assign highest maskable interrupt priority to the real-time interrupt timer ($FFF0). If an unimplemented vector address or a non-I-masked vector ad- dress (value higher than $F2) is written, then IRQ will be the default highest priority interrupt. 9.4 Resets There are four possible sources of reset. Power-on reset (POR), and external reset on the RESET pin share the normal reset vector. The computer operating properly (COP) reset and the clock monitor reset each has a vector. Entry into reset is asynchronous and does not require a clock but the MCU cannot sequence out of reset without a system clock. 9.4.1 Power-On Reset A positive transition on VDD causes a power-on reset (POR). An external voltage level detector, or other external reset circuits, are the usual source of reset in a system. The POR circuit only initializes internal circuitry during cold starts and cannot be used to force a reset as system voltage drops. 9.4.2 External Reset The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic one in less than eight E-clock cycles after an internal device releases reset. When a reset condition is sensed, the RESET pin is driven low by an internal device for about 16 E-clock cycles, then released. Eight E-clock cycles later it is sampled. If the pin is still held low, the CPU assumes that an external reset has occurred. If the pin is high, it indicates that the reset was initiated internally by either the COP system or the clock monitor. To prevent a COP or clock monitor reset from being detected during an external reset, hold the reset pin low for at least 32 cycles. An external RC power-up delay circuit on the reset pin is not recommended — circuit charge time can cause the MCU to misinterpret the type of reset that has occurred. 9.4.3 COP Reset The MCU includes a computer operating properly (COP) system to help protect against software fail- ures. When COP is enabled, software must write $55 and $AA (in this order) to the COPRST register in order to keep a watchdog timer from timing out. Other instructions may be executed between these writes. A write of any value other than $55 or $AA or software failing to execute the sequence properly causes a COP reset to occur. 9.4.4 Clock Monitor Reset If clock frequency falls below a predetermined limit when the clock monitor is enabled, a reset occurs. 9.5 Effects of Reset When a reset occurs, MCU registers and control bits are changed to known start-up states, as follows. 9.5.1 Operating Mode and Memory Map Operating mode and default memory mapping are determined by the states of the BKGD, MODA, and MODB pins during reset. The SMODN, MODA, and MODB bits in the MODE register reflect the status of the mode-select inputs at the rising edge of reset. Operating mode and default maps can subsequent- ly be changed according to strictly defined rules. 9.5.2 Clock and Watchdog Control Logic The COP watchdog system is enabled, with the CR[2:0] bits set for the shortest duration time-out. The clock monitor is disabled. The RTIF flag is cleared and automatic hardware interrupts are masked. The rate control bits are cleared, and must be initialized before the RTI system is used. The DLY control bit is set to specify an oscillator start-up delay upon recovery from STOP mode. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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