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MC68HC912BL16 Datasheet(PDF) 49 Page - NXP Semiconductors |
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MC68HC912BL16 Datasheet(HTML) 49 Page - NXP Semiconductors |
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49 / 128 page  MC68HC912BL16TS/D 49 8 EEPROM The MC68HC912BL16 EEPROM serves as a 512-byte nonvolatile memory which can be used for fre- quently accessed static data or as fast access program code. The MC68HC912BL16 EEPROM is arranged in a 16-bit configuration. The EEPROM array may be read as either bytes, aligned words or misaligned words. Access times is one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations. Programming is by byte or aligned word. Attempts to program or erase misaligned words will fail. Only the lower byte will be latched and programmed or erased. Programming and erasing of the user EE- PROM can be done in all operating modes. Each EEPROM byte or aligned word must be erased before programming. The EEPROM module sup- ports byte, aligned word, row (32 bytes) or bulk erase, all using the internal charge pump. Bulk erasure of odd and even rows is also possible in test modes; the erased state is $FF. The EEPROM module has hardware interlocks which protect stored data from corruption by accidentally enabling the program/ erase voltage. Programming voltage is derived from the internal VDD supply with an internal charge pump. The EEPROM has a minimum program/erase life of 10,000 cycles over the complete operating temperature range. 8.1 EEPROM Programmer’s Model The EEPROM module consists of two separately addressable sections. The first is a four-byte memory mapped control register block used for control, testing and configuration of the EEPROM array. The second section is the EEPROM array itself. At reset, the four-byte register section starts at address $00F0 and the EEPROM array is located from addresses $0E00 to $0FFF (see Figure 11). For information on remapping the register block and EE- PROM address space, refer to 5 Operating Modes and Resource Mapping. Read access to the memory array section can be enabled or disabled by the EEON control bit in the INITEE register. This feature allows the access of memory mapped resources that have lower priority than the EEPROM memory array. EEPROM control registers can be accessed and EEPROM locations may be programmed or erased regardless of the state of EEON. Using the normal EEPROG control, it is possible to continue program/erase operations during WAIT. For lowest power consumption during WAIT, stop program/erase by turning off EEPGM. If the STOP mode is entered during programming or erasing, program/erase voltage will be automati- cally turned off and the RC clock (if enabled) is stopped. However, the EEPGM control bit will remain set. When STOP mode is terminated, the program/erase voltage will be automatically turned back on if EEPGM is set. At bus frequencies below 1 MHz, the RC clock must be turned on for program/erase. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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