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MC68HC912BL16 Datasheet(PDF) 45 Page - NXP Semiconductors |
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MC68HC912BL16 Datasheet(HTML) 45 Page - NXP Semiconductors |
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45 / 128 page  MC68HC912BL16TS/D 45 Figure 8 Erase Sequence Flow START ERASE SET LAT SET ERAS WRITE TO ARRAY SET ENPE READ NO ARRAY FAILED TO ERASE ARRAY CLEAR MARGIN FLAG INCREMENT nEP COUNTER DECREMENT nEP COUNTER NO YES YES TURN ON VFP DELAY FOR DURATION OF ERASE PULSE (tEPULSE) CLEAR ENPE DELAY BEFORE VERIFY IS MARGIN FLAG SET? NO YES NO YES ARRAY ERASED? SET MARGIN FLAG nEP = 0? TURN OFF VFP (tVERASE) nEP = 5? YES NO ARRAY ERASED CLEAR ERASE PULSE COUNTER (nEP) CLEAR LAT ARRAY ERASED? Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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