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MC68HC912BL16 Datasheet(PDF) 32 Page - NXP Semiconductors |
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MC68HC912BL16 Datasheet(HTML) 32 Page - NXP Semiconductors |
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32 / 128 page  MC68HC912BL16 32 MC68HC912BL16TS/D 6 Bus Control and Input/Output Internally the MC68HC912BL16 has full 16-bit data paths, but depending upon the operating mode and control registers, the external bus may be eight or sixteen bits. There are cases where 8-bit and 16-bit accesses can appear on adjacent cycles using the LSTRB signal to indicate 8- or 16-bit data. 6.1 Detecting Access Type from External Signals The external signals LSTRB, R/W, and A0 can be used to determine the type of bus access that is tak- ing place. Accesses to the internal RAM module are the only type of access that produce LSTRB=A0=1, because the internal RAM is specifically designed to allow misaligned 16-bit accesses in a single cycle. In these cases the data for the address that was accessed is on the low half of the data bus and the data for address + 1 is on the high half of the data bus (data order is swapped). 6.2 Registers Not all registers are visible in the MC68HC912BL16 memory map under certain conditions. In special peripheral mode the first 16 registers associated with bus expansion are removed from the memory map. In expanded modes, some or all of port A, port B, and port E are used for expansion buses and control signals. In order to allow emulation of the single-chip functions of these ports, some of these registers must be rebuilt in an external port replacement unit. In any expanded mode port A and port B are used for address and data lines so registers for these ports, as well as the data direction registers for these ports, are removed from the on-chip memory map and become external accesses. In any expanded mode, port E pins may be needed for bus control (e.g., ECLK, R/W). To regain the single-chip functions of port E, the emulate port E (EME) control bit in the MODE register may be set. In this special case of expanded mode and EME set, PORTE and DDRE registers are removed from the on-chip memory map and become external accesses so port E may be rebuilt externally. Table 13 Access Type vs. Bus Control Pins LSTRB A0 R/W Type of Access 1 0 1 8-bit read of an even address 0 1 1 8-bit read of an odd address 1 0 0 8-bit write to an even address 0 1 0 8-bit write to an odd address 0 0 1 16-bit read of an even address 1 1 1 16-bit read of an odd address (low/high data swapped) 0 0 0 16-bit write to an even address 1 1 0 16-bit write to an even address (low/high data swapped) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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