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MC9S12K Datasheet(PDF) 3 Page - NXP Semiconductors |
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MC9S12K Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 12 page MC9S12K-Family © MOTOROLA 2003 Rev 6.0, 21-Oct-03 3 • Pin out explanations: — A/D is the number of A/D channels. — I/O is the sum of ports capable to act as digital input or output. 112 Pin Packages: Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 7, M = 8, P = 8, S = 8, T = 8, PAD = 16 input only. 22 inputs provide Interrupt capability (H =8, P= 8, J = 4, IRQ, XIRQ) 80 Pin Packages: Port A = 8, B = 8, E = 6 + 2 input only, J = 2, M = 6, P = 7, S = 4, T = 8, PAD = 8 input only. 11 inputs provide Interrupt capability (P= 7, J = 2, IRQ, XIRQ) — CAN0 can be routed under software control from PM1:0 to pins PM3:2 or PM5:4. — CAN4 pins are shared between IIC pins. — CAN4 can be routed under software control from PJ7:6 to pins PM5:4 or PM7:6. — Versions with 2 CAN modules will have CAN0 and CAN4. — Versions with one CAN module will have CAN0. — Versions with 2 SPI modules will have SPI0 and SPI1. — Versions with 1 SPI will have SPI0. — SPI0 can be routed to either Ports PS7:4 or PM5:2. — SPI2 pins are shared with PWM7:4. — In 112 pin versions SPI2 can be routed under software control to PH7:4. — In 80 pin versions SS signal of SPI2 is not bonded out! Table 1 List of MC9S12K-Family members Flash RAM EEPROM Package Device CAN SCI SPI IIC A/D PWM I/O 256K 12K 4K 112LQFP KT256 3 2 3 1 16 8 91 KG256 2 2 3 1 16 8 91 80QFP KG256 2 2 3 1 8 7 59 128K 8K 2K 112LQFP KG128 2 2 3 1 16 8 91 80QFP KG128 2 2 3 1 8 7 59 64K 4K 1K 112LQFP K64 1 2 2 1 16 8 91 80QFP K64 122 1 87 59 32K 2K 1K 80QFP K32 1 2 1 0 8 7 59 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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