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DA14530 Datasheet(PDF) 39 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 39 Page - Renesas Technology Corp |
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39 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 39 of 332 © 2021 Renesas Electronics Table 25: Power Domains Description Domain Name Description PD_AON Always powered domain. It contains a Clock-less Wake Up controller and the pad-ring. PD_SLP Sleep power domain. It comprises the Arm/WIC, the BLE Timer, the PMU/Clock Generation, the Clocked Wakeup Controller, the Quadrature Decoder, and various registers required for the Wake-Up sequence. PD_SYS System Power Domain. It comprises the AHB bus, the OTP cell and controllers, the ROM, the System RAM, the Watchdog, the SW Timer, and the GPIO port multiplexing. PD_TIM Timer Power Domain. It comprises the RTC and the Timer1. These two blocks can be active during sleep modes. PD_RAD Radio Power Domain. It comprises the BLE Core and the digital PHY of the Radio. 4.2.2.2 Power Modes There are five different power modes in the DA14530: ● Active mode: System is active and operates at full speed ● Sleep mode: No power gating has been programmed. The Cortex CPU is idle, waiting for an interrupt. PD_SYS is on. PD_TIM and PD_RAD depend on the programmed enabled value ● Extended Sleep mode: PD_AON, PD_SLP, and conditionally PD_TIM are active. RAM is expected to be retained for ○ Keeping a BLE connection alive (stack variables or BLE data) ○ Potentially keep the application code and it can be omitted if the OTP is instructed to automatically get mirrored into RAM upon every wake up ● Deep Sleep mode: Shipping clocked mode with all domains disabled. RAM may or may not be retained. RTC operation is programmable ● Hibernation mode: Shipping clock-less mode with all domains disabled. RAM may or may not be retained. No clock is running A summary of the power modes, the digital power domains, as well as the clocks and wake-up capabilities are explained in Table 26. |
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