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DA14530 Datasheet(PDF) 22 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 22 Page - Renesas Technology Corp |
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22 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 22 of 332 © 2021 Renesas Electronics Pin no. Pin Name Type Reset State Description Contains state retention mechanism during power down. 9 P0_10 DIO (Type A) I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. SWDIO DIO INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and control communication (by default). 8 P0_11 DIO (Type A) I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. Debug Interface 9 SWDIO DIO I-PD INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and control communication. Mapped on P0_10 (by default). 12 SWCLK DIO I-PD INPUT JTAG clock signal. Mapped on P0_2 (by default). Clocks 3 XTAL32Mp AI INPUT. Crystal input for the 32 MHz XTAL. 4 XTAL32Mm AO OUTPUT. Crystal output for the 32 MHz XTAL. 13 XTAL32kp AI INPUT. Crystal input for the 32.768 kHz XTAL. Mapped on P0_3. 14 XTAL32km AO OUTPUT. Crystal output for the 32.768 kHz XTAL. Mapped on P0_4. Quadrature Decoder QD_CHA_X DI INPUT. Channel A for the X axis. Mapped on Px ports. QD_CHB_X DI INPUT. Channel B for the X axis. Mapped on Px ports. QD_CHA_Y DI INPUT. Channel A for the Y axis. Mapped on Px ports. QD_CHB_Y DI INPUT. Channel B for the Y axis. Mapped on Px ports. QD_CHA_Z DI INPUT. Channel A for the Z axis. Mapped on Px ports. QD_CHB_Z DI INPUT. Channel B for the Z axis. Mapped on Px ports. SPI Bus Interface SPI_CLK DO INPUT/OUTPUT. SPI Clock. Mapped on Px ports. SPI_DI DI INPUT. SPI Data input. Mapped on Px ports (Note 1). SPI_DO DO OUTPUT. SPI Data output. Mapped on Px ports (Note 2). SPI_EN DI/DO INPUT/OUTPUT. SPI Clock enable. Mapped on Px ports. |
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