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DA14530 Datasheet(PDF) 100 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 100 Page - Renesas Technology Corp |
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100 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 100 of 332 © 2021 Renesas Electronics The quadrature decoder operates on the system clock. The QDEC_CLOCKDIV register defines the number of clock cycles during which the decoding logic samples the data on the channel inputs. The division is automatically disabled when the lp_clk is used as the system clock. 16.3 Programming To program the quadrature decoder for actual quadrature counting or edge counting, follow the simple sequence of steps below: 1. Configure the clock frequency by configuring the QDEC_CLOCKDIV register. The value in this register will be dividing the sys_clk. However, if sys_clk = lp_clk, this divider is completely bypassed. 2. Define which pin pairs represent the different channels for the X, Y, and Z axes or the GPIOs from which the edges are counted. Configure such information at QDEC_CHX_PORT_SEL, QDEC_CHY_PORT_SEL, and QDEC_CHZ_PORT_SEL registers. 3. Configure the interrupt threshold upon which an interrupt will be generated at QDEC_CTRL_REG[QDEC_IRQ_THRES]. Note that the interrupt threshold is based on the value of QDEC_EVENT_CNT_REG which keeps on counting after the interrupt is generated. 4. Define the mode of operation by configuring the respective QDEC_CHx_EVENT_MODE field in the QDEC_CTRL2_REG. 5. Enable the clock of the block by writing at CLK_PER_REG[QUAD_ENABLE]. 6. Wait for the interrupt and then read X, Y, and Z values at QDEC_XCNT_REG, QDEC_YCNT_REG, and QDEC_ZCNT_REG (in the quadrature counting case) or the QDEC_EVENT_CNT_REG (in the edges counting case). 7. Clear the interrupt (by writing at QDEC_CTRL_REG[QDEC_IRQ_STATUS]) and the edge counter (by writing at QDEC_CTRL_REG[QDEC_EVENT_CNT_CLR) if needed. |
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