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DA14530 Datasheet(PDF) 1 Page - Renesas Technology Corp

Part # DA14530
Description  Low Power Bluetooth 5.1 SoC
Download  333 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DA14530 Datasheet(HTML) 1 Page - Renesas Technology Corp

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DA14530
Low Power Bluetooth 5.1 SoC
Final
Datasheet
Revision 3.4
21-Dec-2021
CFR0011-120-00
1 of 332
© 2021 Renesas Electronics
General Description
The DA14530 is an ultra-low power SoC integrating a 2.4 GHz transceiver and an Arm® Cortex-M0+
microcontroller with a RAM of 48 kB and a One-Time Programmable (OTP) memory of 32 kB. It can
be used as a standalone application processor or as a data pump in hosted systems.
The radio transceiver, the baseband processor, and the qualified Bluetooth® low energy stack is fully
compliant with the Bluetooth® Low Energy 5.1 standard.
The DA14530 has dedicated hardware for the Link Layer implementation of BLE and interface
controllers for enhanced connectivity capabilities.
The BLE firmware includes the L2CAP service layer protocols, Security Manager (SM), Attribute
Protocol (ATT), the Generic Attribute Profile (GATT), and the Generic Access Profile (GAP). All
profiles published by the Bluetooth® SIG as well as custom profiles are supported.
The device is suitable for disposables, wireless sensor nodes, beacons, proximity tags and trackers,
smart HID devices (stylus, keyboards, mice, and trackpads), toys, and medical and industrial
applications.
Key Features
■ Compatible with Bluetooth v5.1, ETSI EN 300
328 and EN 300 440 Class 2 (Europe), FCC
CFR47 Part 15 (US) and ARIB STD-T66
(Japan)
■ Supports up to three BLE connections
■ Typical cold boot to radio active 35 ms
■ Processing power
□ 16 MHz 32-bit Arm® Cortex-M0+ with
SWD interface
□ 18300 EEMBC IoTMark-BLE® score
□ Dedicated Link Layer and AES-128
Encryption Processor
□ Software-based True Random Number
Generator (TRNG)
■ Memories
□ 32 kB One-Time-Programmable (OTP)
□ 48 kB Retainable System RAM
□ 144 kB ROM
■ Power management
□ Integrated core LDO with sleep mode
□ Clock-less hibernation mode 300 nA
□ Built-in temperature sensor for die
temperature monitoring
■ Clocks
□ 32 MHz crystal and 32 MHz RC osc.
□ 32 kHz crystal and 32/512 kHz RC osc.
□ 15 kHz RCX as crystal replacement
■ Programmable Reset Circuitry
■ 2× General purpose Timers with capture and
PWM capabilities
■ Digital interfaces
□ 12 GPIOs
□ 2× UARTs (one with flow control)
□ SPI Master/Slave up to 32 MHz (Master)
□ I2C bus at 100 kHz and 400 kHz
□ 3-axis capable Quadrature Decoder
□ Keyboard controller
■ Analog interfaces
□ 4-channel 10-bit ADC
■ Radio transceiver
□ Fully integrated 2.4 GHz CMOS
transceiver
□ Single wire antenna
□ TX: 9 mA, RX: 5 mA (system currents with
VBAT =3 V and 0 dBm)
□ Programmable transmit output power from
-19.5 dBm to +2.5 dBm
□ -94 dBm receiver sensitivity
■ Packages:
□ FCGQFN 24 pins, 2.2 × 3, 0.4 mm pitch


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