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DA14530 Datasheet(PDF) 96 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 96 Page - Renesas Technology Corp |
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96 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 96 of 332 © 2021 Renesas Electronics Table 43: SPI Timing Parameters Parameter Description Typ Unit tCKPER spi_clk clock period 60 ns tCSST CS active time before the first edge of spi_clk 1 spi_clk cycle tCSHOLD CS non-active time after the last edge of spi_clk 1 spi_clk cycle tMOST Master input data latching setup time (spi_clk/2) - 5 ns tMOHOLD Master input data hold time 0 ns tSODEL Slave output data delay 25 ns 15.3 Programming 15.3.1 Master Mode To configure the SPI controller in master mode, follow the steps below: 1. Set the appropriate GPIO ports in SPI clock mode (output), SPI Chip Select mode (output), SPI Data Out mode (output), and SPI Data In mode (input). 2. Enable SPI clock by setting CLK_PER_REG[SPI_ENABLE] = 1. 3. Reset SPI FIFO by setting SPI_CTRL_REG[SPI_FIFO_RESET] = 1. 4. Set the SPI clock mode (synchronous or asynchronous with APB clock) by programming SPI_CLOCK_REG[SPI_MASTER_CLK_MODE]. 5. Set the SPI clock frequency by programming SPI_CLOCK_REG[SPI_CLK_DIV]. If SPI_CLK_DIV is not 0x7F, SPI_CLK = module_clk/2 × (SPI_CLK_DIV + 1). If SPI_CLK_DIV = 0x7F, SPI_CLK = module_clk. 6. Set the SPI mode (CPOL or CPHA) by programming SPI_CONFIG_REG[SPI_MODE]. 7. Set the SPI controller in master mode by setting SPI_CONFIG_REG[SPI_SLAVE_EN] = 0. 8. Define the SPI word length (from 4-bit to 32-bit) by programming SPI_CONFIG_REG[SPI_WORD_LENGTH]. SPI_WORD_LENGTH = word length - 1. To read/write the following sequence has to be performed: 1. If a slave device is slow and does not give the data at the correct clock edge, configure the SPI module to capture data at the next clock edge by setting SPI_CTRL_REG[SPI_CAPTURE_AT_NEXT_EDGE] = 1. Otherwise, set SPI_CTRL_REG[SPI_CAPTURE_AT_NEXT_EDGE] = 0. 2. Release FIFO reset by setting SPI_CTRL_REG[SPI_FIFO_RESET] = 0. 3. Enable SPI TX path by setting SPI_CTRL_REG[SPI_TX_EN] = 1. 4. Enable SPI RX path by setting SPI_CTRL_REG[SPI_RX_EN] = 1. 5. Enable the SPI chip select by programming the SPI_CS_CONFIG_REG[SPI_CS_SELECT] = 1 or 2. This option allows the master to select the slave that is connected to the GPIO that has the function of SPI_CS0 or SPI_CS1. 6. Enable the SPI controller by setting SPI_CTRL_REG[SPI_EN] = 1. 7. Write to TX FIFO by programming SPI_FIFO_WRITE_REG[SPI_FIFO_WRITE]. Write access is permitted only when SPI_FIFO_STATUS_REG[SPI_TX_FIFO_FULL] = 0. 8. Read from RX FIFO by programming SPI_FIFO_READ_REG[SPI_FIFO_READ]. Read is permitted only when SPI_FIFO_STATUS_REG[SPI_RX_FIFO_EMPTY] = 0. 9. To disable the SPI chip select, set SPI_CS_CONFIG_REG[SPI_CS_SELECT] = 0 to deselect the slave and set SPI_CTRL_REG[SPI_FIFO_RESET] = 1 to reset the SPI FIFO. |
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