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DA14530 Datasheet(PDF) 95 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 95 Page - Renesas Technology Corp |
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95 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 95 of 332 © 2021 Renesas Electronics 15.2 Architecture The SPI controller is an APB peripheral operating on the apb_clk clock. It contains a front end which is clocked by the spi_clk clock and is responsible for the serialization/deserialization of the data in the RX and TX streams. Two separate FIFOs, each of eight bits wide and four bytes deep, are used to store data for RX and TX streams. Since a SPI word can be configured to be from four bits to up to 32 bits, one to four FIFO positions can be written/read at the same time. FIFOs contain logic implementing programmable thresholds comparison. The SPI controller supports DMA requests and interrupt generation based on the FIFO thresholds. If enabled, a DMA request and/or interrupt will be asserted with whether TX_FIFO level is low or RX_FIFO level is high. The SPI interface supports all four modes of operation and the corresponding polarity (CPOL) and phase (CPHA) of the SPI clock (SPI_CLK) are defined in Table 42. Table 42: SPI Modes Configuration and SCK States SPI Mode CPOL CHPA TX SPI_CLK RX SPI_CLK Idle SPI_CLK 0 0 0 Falling edge Rising edge Low 1 0 1 Rising edge Falling edge Low 2 1 0 Rising edge Falling edge High 3 1 1 Falling edge Rising edge High To read from or to write to an external single byte FLASH device in the SPI master mode, a byte swap mechanism is implemented to allow for a proper placement of the bytes in a 16-bit word for the DMA to write to/read from the internal RAM. More specifically, when the SPI controller is configured as a master with DMA support and a 16-bit word width so that the bus utilization is increased compared to reading from an 8-bit device, the byte swap mechanism brings the least significant byte read and place it in the most significant byte in the 16-bit word. The controller automatically swaps the bytes to allow for placing the first byte read in the least significant byte of the 16-bit word. This feature is programmable via SPI_CTRL_REG[SPI_SWAP_BYTES]. The SPI controller can operate at the highest speed (32 MHz on the SPI_CLK line) in a special master mode. The clock of the controller is then either the XTAL32M or the RC32M and can be used for fast booting from external FLASH devices that support this frequency. 15.2.1 SPI Timing The timing of the SPI interface when the SPI controller is in slave mode is presented in Figure 41. Figure 41: SPI Slave Mode Timing (CPOL = 0, CPHA = 0) |
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