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DA14530 Datasheet(PDF) 94 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 94 Page - Renesas Technology Corp |
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94 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 94 of 332 © 2021 Renesas Electronics 15 SPI Interface 15.1 Introduction This controller implements the Serial Peripheral Interface (SPI™)1 for master and slave modes. The serial interface can transmit and receive from four bits to up to 32 bits in master/slave mode. The controller comprises separate TX and RX FIFOs and DMA handshake support. Slave mode clock speed is independent from the system clock speed. Moreover, master's clock speed can be as fast as the system's clock speed. The controller can generate an interrupt upon data threshold reached in the TX or RX FIFOs. Features ● Slave and master mode ● From 4-bit to up to 32-bit operation ● SPI Master clock line speed up to 32 MHz, SPI Slave clock line speed up to 16 MHz ● SPI mode 0, 1, 2, and 3 support (clock edge and phase) ● Built-in separate 8-bit wide and 4-byte deep RX/TX FIFOs for continuous SPI bursts ● Maskable interrupt generation based on TX or RX FIFO thresholds ● DMA support Configuration registers RX fifo 8bits width Y depth TX buffer RX buffer TX shift register RX shift register TX fifo 8bits width X depth Spi core DMA_RX_ACK DMA_TX_ACK DMA_RX_REQ DMA_TX_REQ INTERRUPT APB Figure 40: SPI Block Diagram 1 SPI is a trademark of Motorola, Inc. |
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