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DA14530 Datasheet(PDF) 93 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 93 Page - Renesas Technology Corp |
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93 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 93 of 332 © 2021 Renesas Electronics 3. Enable access to Divisor Latch Registers (DLL and DLH) by setting the UARTx_LCR_REG[UART_DLAB] bit. 4. Set the desired baud rate. To calculate the registers values for the desired baud rate, use the following equation: Divisor=UARTCLK/(16×Baudrate) (3) a. UARTx_IER_DLH_REG: High byte of the Divisor integer part. b. UARTx_RBR_THR_DLL_REG: Low byte of the Divisor integer part. c. UARTx_DLF_REG: The fractional part of the Divisor. 5. Configure the break control bit, parity, number of stop bits, and data length (UARTx_LCR_REG). 6. Enable and configure the FIFO (UARTx_IIR_FCR_REG). 7. Configure the generated interrupts, if needed (UARTx_IER_DLH_REG). 8. Send a byte: a. Check if Transmit Hold Register (THR) is empty (UARTx_LSR_REG[UART_THRE]). b. Load the byte to THR (UARTx_RBR_THR_DLL_REG). c. Check if the byte has been transmitted (UARTx_LSR_REG[UART_TEMT]). 9. Receive a byte: a. Wait until serial data is ready (UARTx_LSR_REG[UART_DR]). b. Read the incoming byte from the THR (UARTx_RBR_THR_DLL_REG). |
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