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DA14530 Datasheet(PDF) 92 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 92 Page - Renesas Technology Corp |
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92 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 92 of 332 © 2021 Renesas Electronics TX FIFO EMPTY? N Y CLEAR INTR THRE Interrupt Enabled? Y N SET INTR TX FIFO Not Empty or IIR Read? Y For the THRE interrupt to be controlled as shown here, the following must be true: - FIFO_MODE!=NONE - THRE_MODE==Disabled - FIFOs disabled (FCR[0]==0) - THRE mode disabled (IER[7]==0) Under the condition that there are no other pending interrupts, the interrupt signal (intr) is asserted N Figure 39: Flowchart of Interrupt Generation When Not in Programmable THRE Interrupt Mode 14.2.5 Shadow Registers The shadow registers shadow some of the existing register bits that are regularly modified by software. These can be used to reduce the software overhead that is introduced by having to perform read-modify-writes. ● UART_SRBR_REG support a host burst mode where the host increments its address but still accesses the same receive buffer register ● UART_STHR support a host burst mode where the host increments its address but still accesses the same transmit holding register ● UART_SFE_REG accesses the FCR[0] register without accessing the other UART_FCR_REG bits ● UART_SRT_REG accesses the FCR[7-6] register without accessing the other UART_FCR_REG bits ● UART_STER_REG accesses the FCR[5-4] register without accessing the other UART_FCR_REG bits 14.2.6 Direct Test Mode The on-chip UARTs can be used for the Direct Test Mode required for the final product PHY layer testing. It can be done either over the HCI layer, which engages a full CTS/RTS UART, or by using a 2-wire UART directly as described in the Bluetooth Low Energy Specification (Volume 6, Part F). 14.3 Programming To configure and use the UART controllers, follow the simple sequence of steps below: 1. Set up the GPIOs to be used for the UART interface (P0x_MODE_REG[PID] = 1 to 4 and/or 19- 20). 2. Enable the selected UART by setting the CLK_PER_REG[UARTx_ENABLE] bit. |
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