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DA14530 Datasheet(PDF) 90 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 90 Page - Renesas Technology Corp |
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90 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 90 of 332 © 2021 Renesas Electronics Table 41: UART Interrupt Priorities Interrupt ID Bits [3-0] Interrupt Set and Reset Functions Priority Interrupt Type Interrupt Source Interrupt Reset Control 0001 - None 0110 Highest Receiver Line status Overrun/parity/framing errors or break interrupt Reading the line status register 0100 1 Receiver Data Available Receiver data available (non- FIFO mode or FIFOs disabled) or RCVR FIFO trigger level reached (FIFO mode and FIFOs enabled) Reading the receiver buffer register (non-FIFO mode or FIFOs disabled) or the FIFO drops below the trigger level (FIFO mode and FIFOs enabled) 1100 2 Character timeout indication No characters in or out of the RCVR FIFO during the last four character times and there is at least one character in it during this time. Reading the receiver buffer register 0010 3 Transmitter holding register empty Transmitter holding register empty (Prog. THRE Mode disabled) or XMIT FIFO at or below threshold (Prog. THRE Mode enabled). Reading the IIR register to check whether there is an interrupt and what its source is; or, writing into THR (FIFOs or THRE Mode not selected or disabled) or XMIT FIFO above threshold (FIFOs and THRE Mode selected and enabled). 0000 4 Reserved 0111 Lowest Reserved - - 14.2.4 Programmable THRE Interrupt The UART can be configured to have a Programmable THRE Interrupt mode available to increase system performance. When Programmable THRE Interrupt mode is selected, it can be enabled via the Interrupt Enable Register (IER[7]). When FIFOs and the THRE Mode are implemented and enabled, THRE Interrupts are active at and below a programmed transmitter FIFO empty threshold level, as shown in the flowchart in Figure 38. Figure 39 shows the programmed transmitter FIFO empty threshold level, where THRE Interrupts are active when the FIFO is empty. In this case the programmable THRE interrupt mode is disabled. This threshold level is programmed into FCR[5:4]. The available empty thresholds are: empty, 2, ¼, and ½. See UART_FCR_REG for threshold setting details. Selection of the best threshold value depends on the system's ability to begin a new transmission sequence in a timely manner. However, one of these thresholds should prove optimum in increasing system performance by preventing the transmitter FIFO from running empty. In addition to the interrupt change, Line Status Register (LSR[5]) also switches its function from indicating transmitter FIFO empty to FIFO full. This allows software to fill the FIFO in each transmit sequence by polling LSR[5] before writing another character. Instead of waiting until the FIFO is completely empty, the flow becomes "fill transmitter FIFO whenever an interrupt occurs and there is data to transmit". Waiting until the FIFO is empty causes a performance hit whenever the system is too busy to respond immediately. Even if everything else is selected and enabled, if the FIFOs are disabled via FCR[0], the Programmable THRE Interrupt mode is also disabled. When not selected or disabled, THRE |
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