 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DA14530 Datasheet(PDF) 89 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
DA14530 Datasheet(HTML) 89 Page - Renesas Technology Corp |
|
|
89 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 89 of 332 © 2021 Renesas Electronics where the divisor is a 16-bit integer value plus 4-bit fractional value. The divisor range is 0 to 65535,9375 with steps of 1/16. Divisor High 8-bit integer part is in the DLH register. Divisor Low 8-bit integer part is in the DLL register. Divisor 4-bit fractional port is in the DLF register. The registers settings for the common baud rate values are presented in Table 40. Table 40: UART Baud Rate Generation Baud Rate Divider Divisor Latch DLH Reg DLL Reg DLF Reg Actual BR Error (%) 1200 833,333 833,3125 3 65 5 1200,03 0,00 2400 416,667 416,6875 1 160 11 2399,88 0,00 4800 208,333 208,3125 0 208 5 4800,48 0,01 9600 104,167 104,1875 0 104 3 9598,08 0,02 19200 52,083 52,0625 0 52 1 19207,68 0,04 38400 26,042 26,0625 0 26 1 38369,30 0,08 57600 17,361 17,375 0 17 6 57553,96 0,08 115200 8,681 8,6875 0 8 11 115107,91 0,08 230400 4,340 4,3125 0 4 5 231884,06 0,64 460800 2,170 2,1875 0 2 3 457142,86 0,79 921600 1,085 1,0625 0 1 1 941176,47 2,12 1000000 1 1 0 1 0 1000000 0,00 14.2.2 Clock Support The UART has two system clocks (pclk and sclk). Having a second asynchronous serial clock (sclk) allows for accurate serial baud rate settings and meeting APB bus interface requirements. With the two-clock design, a synchronization module is implemented to synchronize all controls and data across the two system clock boundaries. Although a serial clock faster than four-times the pclk does not leave enough time for a complete incoming character to be received and pushed into the receiver FIFO, in most cases the pclk signal is faster than the serial clock and this should never be an issue. The serial clock modules must have time to see new register values and reset their respective state machines. This total time is guaranteed to be no more than eight clock cycles of the slower of the two system clocks. Therefore, no data should be transmitted or received before this maximum time expires after the initial configuration of the UART. 14.2.3 Interrupts The assertion of the UART interrupt (UART_INT) occurs whenever one of the several prioritized interrupt types are enabled and active. The following interrupt types can be enabled with the IER register: ● Receiver Error ● Receiver Data Available ● Character Timeout (in FIFO mode only) ● Transmitter Holding Register Empty at/below threshold (in Programmable THRE interrupt mode) When an interrupt occurs, the master accesses the UART_IIR_REG to determine the source of the interrupt before dealing with it accordingly. These interrupt types are described in more detail in Table 41. |
Similar Part No. - DA14530 |
|
Similar Description - DA14530 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
