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DA14530 Datasheet(PDF) 87 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 87 Page - Renesas Technology Corp |
87 / 333 page DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 87 of 332 © 2021 Renesas Electronics 14 UART 14.1 Introduction The DA14530 contains two instances of the UART block, that is, UART and UART2. The UART is compliant to the industry-standard 16550 and is used for serial communication with a peripheral. Data is written from a master (CPU) over the APB bus to the UART and it is converted to the serial form and transmitted to the destination device. Serial data is also received by the UART and stored for the master (CPU) to read back. There is also DMA support on the UART block, thus the internal FIFOs can be used. Only UART supports the hardware flow control signals (RTS and CTS) and the 9-bit mode. UART UART2 Serial Receiver Serial Transmitter Baud Clock Generator Timeout Detector Sync Block Register Block APB Interface FIFO Block pclk APB Bus uart_clk uart_rx uart_tx rts_n uart_int UART only cts_n } Figure 35: UART Block Diagram Features ● 16-byte transmit and receive FIFOs ● Hardware flow control (CTS/RTS) (UART only) ● Shadow registers to reduce software overhead and a software programmable reset is included ● Transmitter Holding Register Empty (THRE) interrupt mode |
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