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DA14530 Datasheet(PDF) 85 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 85 Page - Renesas Technology Corp |
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85 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 85 of 332 © 2021 Renesas Electronics Arbitration takes place on the SDA line while the SCL line is 1. The master which transmits a 1 while the other master transmits a 0 loses the arbitration and turns off its data output stage. The master that has lost the arbitration can continue to generate clocks until the end of the byte transfer. If both masters are addressing the same slave device, the arbitration could go into the data phase. Figure 33 illustrates the timing of an arbitration between two masters on the bus. Control of the bus is determined by the address or master code and data sent by the competing masters, so there is no central master or any order of priority on the bus. Arbitration is not allowed between the following conditions: ● A RESTART condition and a data bit ● A STOP condition and a data bit ● A RESTART condition and a STOP condition Slaves are not involved in the arbitration process. Figure 33: Multiple Master Arbitration 13.2.5 Clock Synchronization All masters generate their own clock to transfer messages. Data is only valid during the HIGH period of the SCL clock. When two or more masters try to transfer information on the bus at the same time, they must synchronize the SCL clock. Clock synchronization is performed using the wired-AND connection to the SCL signal. When the master transitions the SCL clock to 0, the master starts counting the LOW period of the SCL clock and transitions the SCL clock signal to 1 at the beginning of the next clock period. However, if another master is holding the SCL line to 0, the first master goes into a HIGH wait state until the SCL clock line transitions to 1. All masters then count out their HIGH time and the master with the shortest HIGH time transitions the SCL line to 0. The masters then count out their LOW time and the one with the longest LOW time forces the other master into a HIGH wait state. Therefore, a synchronized SCL clock is generated, which is illustrated in Figure 34. Optionally, slaves may hold the SCL line LOW to slow down the timing on the I2C bus. |
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