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DA14530 Datasheet(PDF) 81 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 81 Page - Renesas Technology Corp |
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81 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 81 of 332 © 2021 Renesas Electronics 13.2.2.1 START and STOP Generation When operating as an I2C master, putting data into the transmit FIFO causes the I2C Controller to generate a START condition on the I2C bus. Allowing the transmit FIFO to empty causes the I2C Controller to generate a STOP condition on the I2C bus. When operating as a slave, the I2C Controller does not generate START or STOP conditions, as per the protocol. However, if a read request is made to the I2C Controller, it holds the SCL line low until read data has been supplied to it. This stalls the I2C bus until read data is provided to the slave I2C Controller, or the I2C Controller slave is disabled by writing a 0 to I2C_ENABLE. 13.2.2.2 Combined Formats The I2C Controller supports transactions in a read and write combined format in both 7-bit and 10-bit addressing modes. The I2C Controller does not support mixed address and mixed address format, that is, a 7-bit address transaction followed by a 10-bit address transaction or vice versa. To initiate combined format transfers, I2C_CON_REG[I2C_RESTART_EN] should be set to 1. With this value set and the I2C Controller operating as a master, when an I2C transfer is completed, the I2C Controller checks the transmit FIFO and executes the next transfer. If the direction of the new transfer differs from the previous one, the combined format is used to issue the transfer. If the transmit FIFO is empty when the current I2C transfer completes, a STOP is issued, and the next transfer is issued after a START condition. 13.2.3 I2C Protocols The I2C Controller has the following protocols: ● START and STOP Conditions ● Addressing Slave Protocol ● Transmitting and Receiving Protocols ● START BYTE Transfer Protocol 13.2.3.1 START and STOP Conditions When the bus is idle, both SCL and SDA signals are pulled high through external pull-up resistors on the bus. When a master wants to start a transmission on the bus, it issues a START condition. This is defined to be a high-to-low transition of the SDA signal while SCL is 1. When the master wants to terminate the transmission, it issues a STOP condition. This is defined to be a low-to-high transition of the SDA line while SCL is 1. Figure 27 shows the timing of the START and STOP conditions. When data is being transmitted on the bus, the SDA line must be stable when SCL is 1. Figure 27: START and STOP Conditions NOTE The signal transitions for the START/STOP conditions (Figure 27) reflect those observed at the output signals of the master driving the I2C bus. Be careful with observing the SDA/SCL signals at the input signals of the slave(s), because unequal line delays may result in an incorrect SDA/SCL timing relationship. |
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