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DA14530 Datasheet(PDF) 80 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 80 Page - Renesas Technology Corp |
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80 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 80 of 332 © 2021 Renesas Electronics ● SDA is the data signal line (Serial Data) ● SCL is the clock signal line (Serial Clock) 13.2.1.1 Bus Transfer Terms The following terms are specific to data transfers that occur to/from the I2C bus. ● START (RESTART). Data transfer begins with a START or RESTART condition. The level of the SDA data line changes from high to low, while the SCL clock line remains high. When this occurs, the bus becomes busy ● STOP. Data transfer is terminated by a STOP condition. This occurs when the level of the SDA data line changes from low to high, while the SCL clock line remains high. When the data transfer has been terminated, the bus is free or idle again. The bus stays busy if a RESTART is generated instead of a STOP condition NOTE START and RESTART conditions are functionally identical. 13.2.2 I2C Behavior The I2C can be only be controlled via SW to be an I2C master, communicating with other I2C slaves. The master is responsible for generating the clock and controlling the transfer of data. The I2C protocol also allows multiple masters to reside on the I2C bus and uses an arbitration procedure to determine the bus ownership. A slave is responsible for either transmitting or receiving data to/from the master. The acknowledgement of data is sent by the device that is receiving data, which can be either a master or a slave. Each slave has a unique address that is determined by the system designer. When a master wants to communicate with a slave, the master transmits a START/RESTART condition that is then followed by the slave’s address and a control bit (R/W) to determine whether the master wants to transmit data or receive data from the slave. The slave then sends an acknowledge pulse (ACK) after the address. If a master-transmitter writes to a slave-receiver, the receiver gets one byte of data. This transaction continues until the master terminates the transmission with a STOP condition. If a master-receiver reads from a slave-transmitter, the slave transmits a byte of data to the master, and the master then acknowledges the transaction with an ACK pulse. This transaction continues until the master terminates the transmission by not acknowledging (NACK) the transaction after the last byte is received, and then the master issues a STOP condition or addresses another slave after issuing a RESTART condition. This behavior is illustrated in Figure 26. Figure 26: Data Transfer on the I2C Bus The I2C is a synchronous serial interface. The SDA line is a bidirectional signal and changes only when the SCL line is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain or open-collector to perform wire-AND functions on the bus. The maximum number of devices on the bus is limited only by the maximum capacitance specification of 400 pF. Data is transmitted in byte packages. |
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