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DA14530 Datasheet(PDF) 8 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 8 Page - Renesas Technology Corp |
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8 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 8 of 332 © 2021 Renesas Electronics 30.2.2 Synthesizer ........................................................................................................ 144 30.2.3 Transmitter......................................................................................................... 144 30.2.4 RFIO .................................................................................................................. 144 30.2.5 Biasing ............................................................................................................... 144 30.2.6 RF Monitoring .................................................................................................... 144 31 Registers .................................................................................................................................... 145 31.1 Analog Miscellaneous Registers....................................................................................... 145 31.2 BLE Core Registers .......................................................................................................... 147 31.3 Clock Generation and Reset Registers............................................................................. 172 31.4 DMA Controller Registers ................................................................................................. 185 31.5 General Purpose ADC Registers ...................................................................................... 199 31.6 General Purpose I/O Registers......................................................................................... 204 31.7 General Purpose Registers............................................................................................... 210 31.8 I2C Interface Registers ..................................................................................................... 213 31.9 Keyboard Registers........................................................................................................... 232 31.10 Miscellaneous Registers ................................................................................................... 236 31.11 OTP Controller Registers .................................................................................................. 239 31.12 Quadrature Decoder Registers ......................................................................................... 245 31.13 Real Time Clock Registers ............................................................................................... 248 31.14 SPI Interface Registers ..................................................................................................... 254 31.15 Timer and Triple PWM Registers...................................................................................... 259 31.16 Timer1 Registers............................................................................................................... 264 31.17 UART Interface Registers ................................................................................................. 267 31.18 Chip Version Registers ..................................................................................................... 322 31.19 Wake-Up Registers ........................................................................................................... 323 31.20 Watchdog Registers.......................................................................................................... 326 32 Ordering Information ................................................................................................................ 328 33 Package Information ................................................................................................................. 329 33.1 Moisture Sensitivity Level (MSL)....................................................................................... 329 33.2 Soldering Information ........................................................................................................ 329 33.3 Package Outlines .............................................................................................................. 329 Revision History .............................................................................................................................. 331 Figures Figure 1: System Diagram..................................................................................................................... 2 Figure 2: DA14530 Block Diagram...................................................................................................... 19 Figure 3: FCGQFN24 Pin Assignment (Top View) ............................................................................. 20 Figure 4: Power Management Unit: Bypass Configuration ................................................................. 38 Figure 5: Digital Power Domains......................................................................................................... 38 Figure 6: Power-Up/Wake-Up/Sleep FSM Diagram............................................................................ 42 Figure 7: Power up/Wake-Up from hibernation ................................................................................... 42 Figure 8: Wake-Up from extended/deep sleep.................................................................................... 43 Figure 9: Go-to-Sleep and Bandgap Refresh...................................................................................... 43 Figure 10: OTP Layout Scheme .......................................................................................................... 44 Figure 11: BootROM Sequence .......................................................................................................... 48 Figure 12: Reset Block Diagram ......................................................................................................... 50 Figure 13: POR Timing Diagram ......................................................................................................... 52 Figure 14: Arm Cortex-M0+ Block Diagram ........................................................................................ 54 |
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