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DA14530 Datasheet(PDF) 76 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 76 Page - Renesas Technology Corp |
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76 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 76 of 332 © 2021 Renesas Electronics NOTE When DMA_INIT is enabled, AINC must be set to 0 and BINC to 1. Memory initialization could also be performed by simply setting AINC to 0 and BINC to 1 without enabling the DMA_INIT, provided that the source address of the memory will not change during the transfer. However, it is not guaranteed that the DMA transfer will not be interrupted by other channels of a higher priority, when they request access to the bus at the same time. 12.2.5 Freezing DMA Channels Each channel of the DMA controller can be temporarily disabled by writing a 1 to bit 4 SET_FREEZE_REG[FRZ_DMA] to freeze all channels. To enable a frozen channel again, write a 1 to bit 4 RESET_FREEZE_REG[FRZ_DMA]. There is no HW protection from erroneous programming of the DMA registers. The on-going Memory-to-Memory transfers (DREQ_MODE = 0) cannot be interrupted, therefore the corresponding DMA channels are frozen after a Memory-to-Memory transfer is completed. 12.3 Programming 12.3.1 Memory to Memory Transfers 1. Set the length of data to be transferred (DMAx_LEN_REG). 2. Set the source address (DMAx_A_START_REG). 3. Set the destination address (DMAx_B_START_REG). 4. Configure the number of transfers until an interrupt is generated (DMAx_INT_REG). 5. Configure transfer options: a. DMAx_CTRL_REG[AINC]: Automatic increment of source address. b. DMAx_CTRL_REG[BINC]: Automatic increment of destination address. c. DMAx_CTRL_REG[BW]: Bus transfer width. d. DMAx_CTRL_REG[IRQ_ENABLE]: Enable the DMA interrupt generation for this channel. 6. Start the DMA transfer by setting the DMAx_CTRL_REG[DMA_ON] bit. 7. Wait until the transfer is finished (DMAx_CTRL_REG[DMA_ON] = 0). 8. Clear the IRQ status bit for channel x in DMA_INT_STATUS_REG. 12.3.2 Peripheral to Memory Transfers 1. Set the length of data to be transferred (DMAx_LEN_REG). 2. Set the source address (DMAx_A_START_REG) to the peripheral Rx register (for example, I2C_DATA_CMD_REG). 3. Set the destination address (DMAx_B_START_REG). This should point to a buffer in memory (for example, SYSRAM). 4. Configure the number of transfers until an interrupt is generated (DMAx_INT_REG). 5. Map the peripheral to the selected channels pair (DMA_REQ_MUX_REG[DMAxy_SEL]). 6. Configure transfer options: a. DMAx_CTRL_REG[AINC]: Disable automatic increment of source address. b. DMAx_CTRL_REG[BINC]: Automatic increment of destination address. c. DMAx_CTRL_REG[BW]: Bus transfer width. d. DMAx_CTRL_REG[DREQ_MODE]: Enable triggering by peripheral DMA request. e. DMAx_CTRL_REG[DMA_PRIO]: Set the channel's priority. f. DMAx_CTRL_REG[IRQ_ENABLE]: Enable the DMA interrupt generation for this channel. |
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