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DA14530 Datasheet(PDF) 74 Page - Renesas Technology Corp |
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DA14530 Datasheet(HTML) 74 Page - Renesas Technology Corp |
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74 / 333 page  DA14530 Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.4 21-Dec-2021 CFR0011-120-00 74 of 332 © 2021 Renesas Electronics Table 38: DMA Served Peripherals Name Direction SPI RX/TX UART RX/TX UART2 RX/TX I2C RX/TX GP-ADC RX 12.2.2 Input/Output Multiplexer The multiplexing of peripheral requests is controlled by DMA_REQ_MUX_REG. Thus, if DMA_REQ_MUX_REG[DMAxy_SEL] is set to a certain (non-reserved) value, the TX/RX request from the corresponding peripheral will be routed to DMA channels y (TX request) and x (RX request), respectively. Similarly, an acknowledging de-multiplexing mechanism is applied. When two or more bit-fields (peripheral selectors) of DMA_REQ_MUX_REG have the same value, the lesser significant selector will be given priority (see also the register's description). 12.2.3 DMA Channel Operation A DMA channel is switched on with bit DMA_ON. This bit is automatically reset if the DMA channel's transfer is finished. The DMA channels can either be triggered by SW or by a peripheral DMA request. If DREQ_MODE is 0, a DMA channel is immediately triggered. If DREQ_MODE is 1, a DMA channel can be triggered by a HW request coming from a selected peripheral. All DMA channels support either level (default) or edge-sensitive requests via the bit-field REQ_SENSE of DMAx_CTRL_REG (x = 0, 1, 2, 3). If this bit-field is set (recommended for Memory- to-UART/UART2 and Memory-to-I2C transfers), the channel detects a positive edge on the request signal of the selected peripheral in order to start up a new transfer cycle. The edge-sensitive requests can be used globally, if desired, for all the peripherals interfacing with the DMA. When DMA starts, data is transferred from address DMAx_A_START_REG to address DMAx_B_START_REG for a length of DMAx_LEN_REG, which can be eight, 16, or 32 bits wide. The address increment is realized with an internal 16-bit counter DMAx_IDX_REG, which is set to 0 when the DMA transfer starts and is compared with the DMAx_LEN_REG after each transfer. The register value is multiplied by the values of the automatic increment of source address (AINC), the automatic increment of destination address (BINC), and bus transfer width (BW) before it is added to DMAx_A_START_REG and DMAx_B_START_REG. AINC or BINC must be 0 for register access. If at the end of a DMA cycle, the DMA start condition is still true, the DMA continues. The DMA stops if DREQ_MODE is low or if DMAx_LEN_REG is equal to the internal index register. This condition also clears the DMA_ON bit if DREQ_MODE is 0 or if DREQ_MODE is set to 1 and CIRCULAR bit is not set. If a hand shaking is attached to the specific DMA channel at the end of a DMA cycle, the channel will be blocked for as long as the peripheral is not ready for the next transaction. If the bit CIRCULAR is set to 1, the DMA controller automatically resets the internal index registers and continues from its starting address without intervention of the Arm Cortex-M0+. If the DMA controller is started with DREQ_MODE = 0, the DMA will always stop, regardless of the state of CIRCULAR. |
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